[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20913


Change subject: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds
......................................................................

[WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds

Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
A src/mainboard/lenovo/x200/acpi/bat_thresh.asl
M src/mainboard/lenovo/x200/dsdt.asl
2 files changed, 60 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20913/1

diff --git a/src/mainboard/lenovo/x200/acpi/bat_thresh.asl b/src/mainboard/lenovo/x200/acpi/bat_thresh.asl
new file mode 100644
index 0000000..6a30008
--- /dev/null
+++ b/src/mainboard/lenovo/x200/acpi/bat_thresh.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2017 Arthur Heymans <arthur at aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+	Field (ERAM, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x03),
+				, 2,
+				BSTP, 1, /* Battery start/stop threshold */
+		Offset (0x24),
+				TSH1, 8, /* Battery1 threshold */
+		Offset (0x25),
+				TSH2, 8 /* Battery2 threshold */
+	}
+
+	/* Set upper threshold on battery1 */
+	Method (SUT1, 1, NotSerialized)
+	{
+		BSTP = 1
+		Local0 = Arg0 | 0x80
+		TSH1 = Local0
+	}
+	/* Set lower threshold on battery1 */
+	Method (SLT1, 1, NotSerialized)
+	{
+		BSTP = 0
+		Local0 = Arg0 | 0x80
+		TSH1 = Local0
+	}
+
+	Method (SUT2, 1, NotSerialized)
+	{
+		BSTP = 1
+		Local0 = Arg0 | 0x80
+		TSH2 = Local0
+	}
+
+	Method (SLT2, 1, NotSerialized)
+	{
+		BSTP = 0
+		Local0 = Arg0 | 0x80
+		TSH2 = Local0
+	}
+}
\ No newline at end of file
diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl
index 0706249..5705033 100644
--- a/src/mainboard/lenovo/x200/dsdt.asl
+++ b/src/mainboard/lenovo/x200/dsdt.asl
@@ -56,4 +56,5 @@
 
 	/* Dock support code */
 	#include "acpi/dock.asl"
+	#include "acpi/bat_thresh.asl"
 }

-- 
To view, visit https://review.coreboot.org/20913
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd
Gerrit-Change-Number: 20913
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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