[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Provide option to use Common MP Init

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20895


Change subject: soc/intel/apollolake: Provide option to use Common MP Init
......................................................................

soc/intel/apollolake: Provide option to use Common MP Init

This patch provides the option to use the common CPU
Mp Init code by selecting a Config Token.

CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT config token can be
selected to use the Common MP Init Code, also where CPU MP Init is
done before FSP-S Init.

And if the config token is not selected, the old way of
implementation will exist, where MP Init is been done after
FSP-S.

CQ-DEPEND=CL:*397551
BUG=none
BRANCH=none
TEST=Build and boot Reef

Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/include/soc/cpu.h
3 files changed, 47 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/20895/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index ec4662c..8eaa319 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -150,7 +150,11 @@
 	.read_resources = DEVICE_NOOP,
 	.set_resources = DEVICE_NOOP,
 	.enable_resources = DEVICE_NOOP,
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
+	.init = DEVICE_NOOP,
+#else
 	.init = apollolake_init_cpus,
+#endif
 	.scan_bus = NULL,
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 22e3c80..cac528c 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -35,6 +35,11 @@
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include <cpu/intel/turbo.h>
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
+#include <fsp/api.h>
+#include <intelblocks/mp_init.h>
+#include <romstage_handoff.h>
+#endif
 
 static const struct reg_script core_msr_script[] = {
 	/* Enable C-state and IO/MWAIT redirect */
@@ -57,7 +62,11 @@
 	REG_SCRIPT_END
 };
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
+void soc_core_init(device_t cpu, const void *microcode)
+#else
 static void soc_core_init(device_t cpu)
+#endif
 {
 	/* Set core MSRs */
 	reg_script_run(core_msr_script);
@@ -69,6 +78,7 @@
 	enable_pm_timer_emulation();
 }
 
+#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
 static struct device_operations cpu_dev_ops = {
 	.init = soc_core_init,
 };
@@ -85,6 +95,7 @@
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
 };
+#endif
 
 /*
  * MP and SMM loading initialization.
@@ -97,6 +108,7 @@
 
 static struct smm_relocation_attrs relo_attrs;
 
+#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
 static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
 {
 	msr_t msr;
@@ -139,6 +151,23 @@
 	/* Make sure BSP is using the microcode from cbfs */
 	intel_microcode_load_unlocked(*microcode);
 }
+#else
+/*
+ * Do essential initialization tasks before APs can be fired up -
+ *
+ * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
+ * that are set prior to ramstage.
+ * Real MTRRs programming are being done after resource allocation.
+ *
+ * Do, FSP loading before MP Init to ensure that the FSP cmponent stored in
+ * external stage cache in TSEG does not flush off due to SMM relocation
+ * during MP Init stage.
+ */
+static void pre_mp_init(void)
+{
+	fsps_load(romstage_handoff_is_resume());
+}
+#endif
 
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
@@ -197,6 +226,14 @@
 	.post_mp_init = smm_southbridge_enable,
 };
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
+void soc_init_cpus(struct bus *cpu_bus, const void *microcode)
+{
+	/* Clear for take-off */
+	if (mp_init_with_smm(cpu_bus, &mp_ops))
+		printk(BIOS_ERR, "MP initialization failure.\n");
+}
+#else
 void apollolake_init_cpus(struct device *dev)
 {
 	/* Clear for take-off */
@@ -208,3 +245,4 @@
 		IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
 		fast_spi_cache_bios_region();
 }
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 10e0595..67d7dc8 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -18,15 +18,17 @@
 #ifndef _SOC_APOLLOLAKE_CPU_H_
 #define _SOC_APOLLOLAKE_CPU_H_
 
+#if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
 #define CPUID_APOLLOLAKE_A0	0x506c8
 #define CPUID_APOLLOLAKE_B0	0x506c9
 #define CPUID_GLK_A0		0x706a0
 #define CPUID_GLK_B0		0x706a1
 
-/* Common Timer Copy (CTC) frequency - 19.2MHz. */
-#define CTC_FREQ		19200000
-
 struct device;
 void apollolake_init_cpus(struct device *dev);
+#endif
+
+/* Common Timer Copy (CTC) frequency - 19.2MHz. */
+#define CTC_FREQ		19200000
 
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */

-- 
To view, visit https://review.coreboot.org/20895
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6
Gerrit-Change-Number: 20895
Gerrit-PatchSet: 1
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170807/ac849611/attachment-0001.html>