[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/20886

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume
......................................................................

soc/intel/skylake: Enable UART debug controller on S3 resume

1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.

2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.

3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.

BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.

Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/uart.c
5 files changed, 27 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20886/2
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Gerrit-Change-Number: 20886
Gerrit-PatchSet: 2
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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