[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add lpss.c to ramstage

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20850


Change subject: soc/intel/common: Add lpss.c to ramstage
......................................................................

soc/intel/common: Add lpss.c to ramstage

BUG=b:64030366

Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/common/block/lpss/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20850/1

diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc
index bb65bfe..50d1c10 100644
--- a/src/soc/intel/common/block/lpss/Makefile.inc
+++ b/src/soc/intel/common/block/lpss/Makefile.inc
@@ -1,3 +1,4 @@
 bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
 verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830
Gerrit-Change-Number: 20850
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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