[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use common I2C code from intelblocks
Rizwan Qureshi (Code Review)
gerrit at coreboot.org
Fri Apr 28 20:50:57 CEST 2017
Rizwan Qureshi has uploaded a new change for review. ( https://review.coreboot.org/19469 )
Change subject: soc/intel/skylake: Use common I2C code from intelblocks
......................................................................
soc/intel/skylake: Use common I2C code from intelblocks
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
Change-Id: Iae7d13303090c72380534618741858502cc9ee33
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/bootblock.c
D src/soc/intel/skylake/bootblock/i2c.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/i2c.c
M src/soc/intel/skylake/include/soc/pci_devs.h
7 files changed, 60 insertions(+), 214 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/19469/6
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 23801b0..c4a961c 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -51,13 +51,13 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
+ select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI
- select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
@@ -317,4 +317,7 @@
int
default 2
+config SKYLAKE_I2C_CTRL_MAX
+ int
+ default 6
endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 171a916..a9c8b01 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -11,7 +11,7 @@
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
-bootblock-y += bootblock/i2c.c
+bootblock-y += i2c.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += bootblock/smbus.c
@@ -32,14 +32,14 @@
verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c
-verstage-y += bootblock/i2c.c
+verstage-y += i2c.c
verstage-y += spi.c
verstage-y += tsc_freq.c
romstage-y += flash_controller.c
romstage-y += gpio.c
romstage-y += gspi.c
-romstage-y += bootblock/i2c.c
+romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += monotonic_timer.c
romstage-y += me.c
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index f386f96..a35f93e 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -15,6 +15,7 @@
#include <bootblock_common.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/lpss_i2c.h>
#include <soc/bootblock.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
@@ -36,6 +37,8 @@
void bootblock_soc_init(void)
{
+ int bus;
+
/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
bootblock_fsp_temp_ram_init();
@@ -48,6 +51,10 @@
report_platform_info();
set_max_freq();
pch_early_init();
- i2c_early_init();
+
+ /* Initialize I2C controllers that are enabled in devicetree */
+ for (bus = 0; bus < CONFIG_SKYLAKE_I2C_CTRL_MAX; bus++)
+ lpss_i2c_early_init_bus(bus);
+
gspi_early_bar_init();
}
diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c
deleted file mode 100644
index f8859a4..0000000
--- a/src/soc/intel/skylake/bootblock/i2c.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <commonlib/helpers.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <device/pci_def.h>
-#include <intelblocks/lpss.h>
-#include <soc/intel/common/lpss_i2c.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/bootblock.h>
-#include "chip.h"
-
-uintptr_t lpss_i2c_base_address(unsigned int bus)
-{
- int devfn;
- pci_devfn_t dev;
-
- /* Find device+function for this controller */
- devfn = i2c_bus_to_devfn(bus);
- if (devfn < 0)
- return 0;
-
- /* Form a PCI address for this device */
- dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
-
- /* Read the first base address for this device */
- return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
-}
-
-static void i2c_early_init_bus(unsigned int bus)
-{
- DEVTREE_CONST struct soc_intel_skylake_config *config;
- DEVTREE_CONST struct device *tree_dev;
- pci_devfn_t dev;
- int devfn;
- uintptr_t base;
-
- /* Find the PCI device for this bus controller */
- devfn = i2c_bus_to_devfn(bus);
- if (devfn < 0)
- return;
-
- /* Look up the controller device in the devicetree */
- dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
- tree_dev = dev_find_slot(0, devfn);
- if (!tree_dev || !tree_dev->enabled)
- return;
-
- /* Skip if not enabled for early init */
- config = tree_dev->chip_info;
- if (!config)
- return;
- if (!config->i2c[bus].early_init)
- return;
-
- /* Prepare early base address for access before memory */
- base = EARLY_I2C_BASE(bus);
- pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
- pci_write_config32(dev, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Take device out of reset */
- lpss_reset_release(base);
-
- /* Initialize the controller */
- lpss_i2c_init(bus, &config->i2c[bus]);
-}
-
-void i2c_early_init(void)
-{
- int bus;
-
- /* Initialize I2C controllers that are enabled in devicetree */
- for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++)
- i2c_early_init_bus(bus);
-}
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index cd461d4..b8f9f84 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -22,31 +22,20 @@
#include <arch/acpi_device.h>
#include <device/i2c.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/lpss_i2c.h>
#include <stdint.h>
#include <soc/gpio_defs.h>
#include <soc/gpe.h>
#include <soc/irq.h>
-#include <soc/intel/common/lpss_i2c.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <soc/vr_config.h>
-#define SKYLAKE_I2C_DEV_MAX 6
-
enum skylake_i2c_voltage {
I2C_VOLTAGE_3V3,
I2C_VOLTAGE_1V8
-};
-
-struct skylake_i2c_config {
- /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
- enum i2c_speed speed;
- /* Bus should be enabled prior to ramstage with temporary base */
- int early_init;
- /* Custom bus speed configuration { scl_lcnt, scl_hcnt, sda_hold } */
- struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
};
struct soc_intel_skylake_config {
@@ -208,8 +197,8 @@
/* I2C */
/* Bus voltage level, default is 3.3V */
- enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
- struct lpss_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX];
+ enum skylake_i2c_voltage i2c_voltage[CONFIG_SKYLAKE_I2C_CTRL_MAX];
+ struct lpss_i2c_bus_config i2c[CONFIG_SKYLAKE_I2C_CTRL_MAX];
/* GSPI */
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c
index 25cc8e8..c4c74d3 100644
--- a/src/soc/intel/skylake/i2c.c
+++ b/src/soc/intel/skylake/i2c.c
@@ -1,104 +1,70 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2016 Google Inc.
+ * Copyright 2017 Google Inc.
+ * Copyright 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-#include <arch/acpigen.h>
+#include <console/console.h>
#include <device/device.h>
-#include <device/i2c.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <soc/intel/common/lpss_i2c.h>
-#include <soc/ramstage.h>
+#include <intelblocks/lpss_i2c.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include "chip.h"
-uintptr_t lpss_i2c_base_address(unsigned int bus)
+const struct lpss_i2c_bus_config *i2c_get_soc_cfg(void)
{
- int devfn;
- struct device *dev;
- struct resource *res;
+ DEVTREE_CONST struct soc_intel_skylake_config *config;
+ int devfn = SA_DEVFN_ROOT;
+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
- /* bus -> devfn */
- devfn = i2c_bus_to_devfn(bus);
- if (devfn >= 0) {
- /* devfn -> dev */
- dev = dev_find_slot(0, devfn);
- if (dev) {
- /* dev -> bar0 */
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res)
- return res->base;
- }
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
}
- return (uintptr_t)NULL;
+ config = dev->chip_info;
+
+ return &config->i2c[0];
}
-static int i2c_dev_to_bus(struct device *dev)
+uintptr_t i2c_get_soc_early_base(unsigned int bus)
{
- return i2c_devfn_to_bus(dev->path.pci.devfn);
+ return EARLY_I2C_BASE(bus);
}
-/*
- * The device should already be enabled and out of reset,
- * either from early init in coreboot or SiliconInit in FSP.
- */
-static void i2c_dev_init(struct device *dev)
+int i2c_soc_devfn_to_bus(unsigned int devfn)
{
- struct soc_intel_skylake_config *config = dev->chip_info;
- int bus = i2c_dev_to_bus(dev);
-
- if (!config || bus < 0)
- return;
-
- lpss_i2c_init(bus, &config->i2c[bus]);
+ switch (devfn) {
+ case PCH_DEVFN_I2C0: return 0;
+ case PCH_DEVFN_I2C1: return 1;
+ case PCH_DEVFN_I2C2: return 2;
+ case PCH_DEVFN_I2C3: return 3;
+ case PCH_DEVFN_I2C4: return 4;
+ case PCH_DEVFN_I2C5: return 5;
+ }
+ return -1;
}
-/* Generate ACPI I2C device objects */
-static void i2c_fill_ssdt(struct device *dev)
+int i2c_soc_bus_to_devfn(unsigned int bus)
{
- struct soc_intel_skylake_config *config = dev->chip_info;
- int bus = i2c_dev_to_bus(dev);
-
- if (!config || bus < 0)
- return;
-
- acpigen_write_scope(acpi_device_path(dev));
- lpss_i2c_acpi_fill_ssdt(bus, &config->i2c[bus]);
- acpigen_pop_len();
+ switch (bus) {
+ case 0: return PCH_DEVFN_I2C0;
+ case 1: return PCH_DEVFN_I2C1;
+ case 2: return PCH_DEVFN_I2C2;
+ case 3: return PCH_DEVFN_I2C3;
+ case 4: return PCH_DEVFN_I2C4;
+ case 5: return PCH_DEVFN_I2C5;
+ }
+ return -1;
}
-
-static struct i2c_bus_operations i2c_bus_ops = {
- .dev_to_bus = &i2c_dev_to_bus,
-};
-
-static struct device_operations i2c_dev_ops = {
- .read_resources = &pci_dev_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .scan_bus = &scan_smbus,
- .ops_pci = &soc_pci_ops,
- .ops_i2c_bus = &i2c_bus_ops,
- .init = &i2c_dev_init,
- .acpi_fill_ssdt_generator = &i2c_fill_ssdt,
-};
-
-static const unsigned short pci_device_ids[] = {
- 0x9d60, 0x9d61, 0x9d62, 0x9d63, 0x9d64, 0x9d65, 0
-};
-
-static const struct pci_driver pch_i2c __pci_driver = {
- .ops = &i2c_dev_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
-};
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 13114f1..f51691c 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -148,34 +148,6 @@
#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
#define PCH_DEV_GBE _PCH_DEV(LPC, 6)
-/* Convert I2C bus number to PCI device and function */
-static inline int i2c_bus_to_devfn(unsigned int bus)
-{
- switch (bus) {
- case 0: return PCH_DEVFN_I2C0;
- case 1: return PCH_DEVFN_I2C1;
- case 2: return PCH_DEVFN_I2C2;
- case 3: return PCH_DEVFN_I2C3;
- case 4: return PCH_DEVFN_I2C4;
- case 5: return PCH_DEVFN_I2C5;
- }
- return -1;
-}
-
-/* Convert PCI device and function to I2C bus number */
-static inline int i2c_devfn_to_bus(unsigned int devfn)
-{
- switch (devfn) {
- case PCH_DEVFN_I2C0: return 0;
- case PCH_DEVFN_I2C1: return 1;
- case PCH_DEVFN_I2C2: return 2;
- case PCH_DEVFN_I2C3: return 3;
- case PCH_DEVFN_I2C4: return 4;
- case PCH_DEVFN_I2C5: return 5;
- }
- return -1;
-}
-
static inline int spi_devfn_to_bus(unsigned int devfn)
{
switch (devfn) {
--
To view, visit https://review.coreboot.org/19469
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Iae7d13303090c72380534618741858502cc9ee33
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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