[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use ITSS common code
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Apr 28 16:32:23 CEST 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19244 )
Change subject: soc/intel/skylake: Use ITSS common code
......................................................................
soc/intel/skylake: Use ITSS common code
This patch uses common ITSS library to setup
itss irq.
Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
Reviewed-on: https://review.coreboot.org/19244
Reviewed-by: Subrata Banik <subrata.banik at intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/include/soc/itss.h
M src/soc/intel/skylake/lpc.c
5 files changed, 22 insertions(+), 45 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
Subrata Banik: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 23801b0..95cf330 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -51,6 +51,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
+ select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 78f31a8..74cdb9c 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -15,10 +15,10 @@
* GNU General Public License for more details.
*/
+#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <soc/iomap.h>
#include <soc/irq.h>
-#include <soc/itss.h>
#include <soc/gpio_defs.h>
#include <soc/gpe.h>
#include <soc/pcr_ids.h>
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 12ce3d0..01bff0b 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,11 +18,11 @@
#include <chip.h>
#include <device/device.h>
#include <device/pci_def.h>
+#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
-#include <soc/itss.h>
#include <soc/lpc.h>
#include <soc/p2sb.h>
#include <soc/pch.h>
@@ -132,8 +132,7 @@
{
const struct device *dev;
const config_t *config;
- u8 index = 0;
- u8 pch_interrupt_routing[MAX_PXRC_CONFIG];
+ uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
if (!dev || !dev->chip_info)
@@ -149,17 +148,10 @@
pch_interrupt_routing[6] = config->pirqg_routing;
pch_interrupt_routing[7] = config->pirqh_routing;
- for (index = 0; index < MAX_PXRC_CONFIG; index++) {
- if (pch_interrupt_routing[index] < 16 &&
- pch_interrupt_routing[index] > 2 &&
- pch_interrupt_routing[index] != 8 &&
- pch_interrupt_routing[index] != 13) {
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index,
- pch_interrupt_routing[index]);
- }
- }
+ itss_irq_init(pch_interrupt_routing);
}
+
static void soc_config_acpibase(void)
{
uint32_t reg32;
diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h
index 0681e9d..5ff9bb1 100644
--- a/src/soc/intel/skylake/include/soc/itss.h
+++ b/src/soc/intel/skylake/include/soc/itss.h
@@ -16,26 +16,8 @@
#ifndef SOC_INTEL_SKL_ITSS_H
#define SOC_INTEL_SKL_ITSS_H
-/* Max PXRC registers in ITSS*/
-#define MAX_PXRC_CONFIG 0x08
-
-/* PIRQA Routing Control Register*/
-#define PCR_ITSS_PIRQA_ROUT 0x3100
-/* PIRQB Routing Control Register*/
-#define PCR_ITSS_PIRQB_ROUT 0x3101
-/* PIRQC Routing Control Register*/
-#define PCR_ITSS_PIRQC_ROUT 0x3102
-/* PIRQD Routing Control Register*/
-#define PCR_ITSS_PIRQD_ROUT 0x3103
-/* PIRQE Routing Control Register*/
-#define PCR_ITSS_PIRQE_ROUT 0x3104
-/* PIRQF Routing Control Register*/
-#define PCR_ITSS_PIRQF_ROUT 0x3105
-/* PIRQG Routing Control Register*/
-#define PCR_ITSS_PIRQG_ROUT 0x3106
-/* PIRQH Routing Control Register*/
-#define PCR_ITSS_PIRQH_ROUT 0x3107
-/* ITSS Power reduction control */
-#define PCR_ITSS_ITSSPRC 0x3300
+#define ITSS_MAX_IRQ 119
+#define IRQS_PER_IPC 32
+#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
#endif /* SOC_INTEL_SKL_ITSS_H */
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index db2b960..f689e1c 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -30,13 +30,13 @@
#include <cpu/cpu.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
+#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <string.h>
#include <soc/acpi.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
-#include <soc/itss.h>
#include <soc/lpc.h>
#include <soc/nvs.h>
#include <soc/pch.h>
@@ -98,15 +98,18 @@
{
device_t irq_dev;
config_t *config = dev->chip_info;
+ uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT, config->pirqa_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQB_ROUT, config->pirqb_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQC_ROUT, config->pirqc_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQD_ROUT, config->pirqd_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQE_ROUT, config->pirqe_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQF_ROUT, config->pirqf_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQG_ROUT, config->pirqg_routing);
- pcr_write8(PID_ITSS, PCR_ITSS_PIRQH_ROUT, config->pirqh_routing);
+ pch_interrupt_routing[0] = config->pirqa_routing;
+ pch_interrupt_routing[1] = config->pirqb_routing;
+ pch_interrupt_routing[2] = config->pirqc_routing;
+ pch_interrupt_routing[3] = config->pirqd_routing;
+ pch_interrupt_routing[4] = config->pirqe_routing;
+ pch_interrupt_routing[5] = config->pirqf_routing;
+ pch_interrupt_routing[6] = config->pirqg_routing;
+ pch_interrupt_routing[7] = config->pirqh_routing;
+
+ itss_irq_init(pch_interrupt_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
@@ -159,12 +162,11 @@
static void clock_gate_8254(struct device *dev)
{
config_t *config = dev->chip_info;
- const uint32_t cge8254_mask = (1 << 2);
if (!config->clock_gate_8254)
return;
- pcr_rmw32(PID_ITSS, PCR_ITSS_ITSSPRC, ~cge8254_mask, cge8254_mask);
+ itss_clock_gate_8254();
}
static void lpc_init(struct device *dev)
--
To view, visit https://review.coreboot.org/19244
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Naveenkrishna Ch <naveenkrishna.ch at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
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