[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Set xtal bypass on low power idle

[Naresh Solanki (Code Review)]

Hello Aaron Durbin, Subrata Banik, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/19442

to look at the new patch set (#5).

Change subject: soc/intel/skylake: Set xtal bypass on low power idle
......................................................................

soc/intel/skylake: Set xtal bypass on low power idle

Whe using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.

Hence set xtal bypass bit in CIR31C for low power idle entry.

TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.

Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pmc.h
2 files changed, 9 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/19442/5
-- 
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rajat Jain <rajatja at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park at intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam at intel.com>