[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19490 )

Change subject: soc/intel/common: Add PCI configuration code for UART
......................................................................

soc/intel/common: Add PCI configuration code for UART

Add PCI configuration code support for intel/common/
block/uart module.

Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/common/block/include/intelblocks/uart.h
M src/soc/intel/common/block/uart/Makefile.inc
M src/soc/intel/common/block/uart/uart.c
3 files changed, 48 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19490/1

diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h
index ed4c7f0..b46edd7 100644
--- a/src/soc/intel/common/block/include/intelblocks/uart.h
+++ b/src/soc/intel/common/block/include/intelblocks/uart.h
@@ -17,8 +17,11 @@
 #define SOC_INTEL_COMMON_BLOCK_UART_H
 
 #include <arch/io.h>
+#include <device/device.h>
 
 void uart_common_init(device_t dev, uintptr_t baseaddr,
 		uint32_t clk_m_val, uint32_t clk_n_val);
 
+void pch_uart_read_resources(struct device *dev);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_UART_H */
diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc
index 13f5da8..0ec5314 100644
--- a/src/soc/intel/common/block/uart/Makefile.inc
+++ b/src/soc/intel/common/block/uart/Makefile.inc
@@ -1 +1,2 @@
-bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
\ No newline at end of file
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
\ No newline at end of file
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 729a31b..d39de9d 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -12,10 +12,15 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
+#include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/uart.h>
+
+__attribute__((weak)) void pch_uart_read_resources(struct device *dev)
+{ /* no-op */ }
 
 void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
 		uint32_t clk_n_val)
@@ -33,3 +38,40 @@
 	/* Set M and N divisor inputs and enable clock */
 	lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
 }
+
+#if ENV_RAMSTAGE
+
+struct pci_operations pci_ops = {
+	.set_subsystem = &pci_dev_set_subsystem
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= &pch_uart_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources		= &pci_dev_enable_resources,
+	.ops_pci		= &pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = {
+	0x9d27, /*Sunrisepoint LP UART0 */
+	0x9d28, /* Sunrisepoint LP UART1 */
+	0x9d66, /* Sunrisepoint LP UART2 */
+	0xa127, /* KBL-H UART0 */
+	0xa128, /* KBL-H UART1 */
+	0xa166, /* KBL-H UART2 */
+	0x5abc, /* Apollolake UART0 */
+	0x5abe, /* Apollolake UART1 */
+	0x5ac0, /* Apollolake UART2 */
+	0x5aee, /* Apollolake UART3 */
+	0x31bc, /* GLK UART0 */
+	0x31be, /* GLK UART1 */
+	0x31c0, /* GLK UART2 */
+	0x31ee, /* GLK UART3 */
+};
+
+static const struct pci_driver pch_uart __pci_driver = {
+	.ops	 = &device_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
+#endif /* ENV_RAMSTAGE */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>