[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/apollolake: Invalidate MRC cache and cold reset

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded a new change for review. ( https://review.coreboot.org/19481 )

Change subject: [WIP]soc/intel/apollolake: Invalidate MRC cache and cold reset
......................................................................

[WIP]soc/intel/apollolake: Invalidate MRC cache and cold reset

As part memory setting change one needs to trigger retrain of the memory.
Cold reset is required for full memory training. Invalidate current cache
as part of the process.

BUG=chrome-os-partner:37490798
BRANCH=None
TEST=RW AU Update using 'chromeos-firmwareupdate'

Change-Id: Ifc98a7c0ae24920110ab0ebc216d55e8ed4f8f97
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/common/mrc_cache.c
M src/soc/intel/common/mrc_cache.h
3 files changed, 19 insertions(+), 3 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/19481/1

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 0270920..d85e325 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -31,6 +31,7 @@
 #include <fsp/api.h>
 #include <fsp/memmap.h>
 #include <fsp/util.h>
+#include <reset.h>
 #include <soc/cpu.h>
 #include <soc/flash_ctrlr.h>
 #include <soc/intel/common/mrc_cache.h>
@@ -262,6 +263,16 @@
 {
 	struct region_device rdev;
 
+	if (mrc_cache_get_current(MRC_TRAINING_DATA, version, &rdev) ==
+			CACHE_METADATA_MISMATCH) {
+		/* 
+		 * Invalidate MRC cache and Cold reset assuming FSP_verion bumped up,
+		 * will do full MRC Training.
+		*/
+		invalidate_normal_cache();
+		hard_reset();
+	}
+
 	fill_console_params(mupd);
 	mainboard_memory_init_params(mupd);
 
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index e0d4b7d..74f7910 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -325,7 +325,7 @@
 	if (version != md.version) {
 		printk(BIOS_INFO, "MRC: version mismatch: %x vs %x\n",
 			md.version, version);
-		return -1;
+		return CACHE_METADATA_MISMATCH;
 	}
 
 	/* Re-size rdev to only contain the data. i.e. remove metadata. */
@@ -486,7 +486,7 @@
 	protect_mrc_cache(DEFAULT_MRC_CACHE);
 }
 
-static void invalidate_normal_cache(void)
+void invalidate_normal_cache(void)
 {
 	struct region_file cache_file;
 	struct region_device rdev;
@@ -494,11 +494,13 @@
 	const uint32_t invalid = ~MRC_DATA_SIGNATURE;
 
 	/* Invalidate only on recovery mode with retraining enabled. */
+//Hack
+#if 0
 	if (!vboot_recovery_mode_enabled())
 		return;
 	if (!vboot_recovery_mode_memory_retrain())
 		return;
-
+#endif
 	if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) {
 		printk(BIOS_ERR, "MRC: Couldn't find '%s' region. Invalidation failed\n",
 			name);
diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h
index 4511fc3..0690700 100644
--- a/src/soc/intel/common/mrc_cache.h
+++ b/src/soc/intel/common/mrc_cache.h
@@ -24,6 +24,8 @@
 	MRC_VARIABLE_DATA,
 };
 
+#define CACHE_METADATA_MISMATCH -2
+
 /*
  * It's up to the caller to decide when to retrieve and stash data. There is
  * differentiation on recovery mode CONFIG_HAS_RECOVERY_MRC_CACHE, but that's
@@ -39,5 +41,6 @@
 				struct region_device *rdev);
 int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 			size_t size);
+void invalidate_normal_cache(void);
 
 #endif /* _COMMON_MRC_CACHE_H_ */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifc98a7c0ae24920110ab0ebc216d55e8ed4f8f97
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>