[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Set xtal bypass on low power idle

[Naresh Solanki (Code Review)]

Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/19442 )

Change subject: soc/intel/skylake: Set xtal bypass on low power idle
......................................................................


Patch Set 4:

(4 comments)

https://review.coreboot.org/#/c/19442/3/src/soc/intel/skylake/finalize.c
File src/soc/intel/skylake/finalize.c:

Line 148: 		reg32 = read32(pmcbase + CIR31C);
> /* Single line comment */
FIxed


Line 150: 		write32(pmcbase + CIR31C, reg32);
> Does this apply equally to skylake as well as kabylake?
Yes.


Line 153: 	/* we should disable Heci1 based on the devicetree policy */
> New line separating next block?
Fixed.


https://review.coreboot.org/#/c/19442/3/src/soc/intel/skylake/include/soc/pmc.h
File src/soc/intel/skylake/include/soc/pmc.h:

PS3, Line 102:   
> tab used here instead of space like the rest of the file.
Fixed


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Gerrit-MessageType: comment
Gerrit-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
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Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
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