[coreboot-gerrit] Change in coreboot[master]: i82801gx: Enable PCI-to-PCI bridge

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/2706 )

Change subject: i82801gx: Enable PCI-to-PCI bridge
......................................................................


i82801gx: Enable PCI-to-PCI bridge

Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.

Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.

The bridge was disable in the following commit [1]

    commit a8e1168064b34b46494b58480411a11bc98340f6
    Author: Stefan Reinauer <stepan at coresystems.de>
    Date:   Wed Mar 11 14:54:18 2009 +0000

        This patch contains some significant updates to the i82801gx component and will
        be required for a series of later patches. Roughly it contains:

but unfortunately it was not noted which system this caused
problems with.

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6

Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Reviewed-on: https://review.coreboot.org/2706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
M src/southbridge/intel/i82801gx/pci.c
1 file changed, 0 insertions(+), 9 deletions(-)

Approvals:
  Paul Menzel: Looks good to me, but someone else must approve
  Stefan Reinauer: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 03e2544..1635dfe 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -58,7 +58,6 @@
 	pci_write_config16(dev, SECSTS, reg16);
 }
 
-#undef PCI_BRIDGE_UPDATE_COMMAND
 static void ich_pci_dev_enable_resources(struct device *dev)
 {
 	const struct pci_operations *ops;
@@ -76,16 +75,8 @@
 
 	command = pci_read_config16(dev, PCI_COMMAND);
 	command |= dev->command;
-#ifdef PCI_BRIDGE_UPDATE_COMMAND
-	/* If we write to PCI_COMMAND, on some systems
-	 * this will cause the ROM and APICs not being visible
-	 * anymore.
-	 */
 	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
-#else
-	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
-#endif
 }
 
 static void ich_pci_bus_enable_resources(struct device *dev)

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Ronald G. Minnich <rminnich at gmail.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer at coreboot.org>
Gerrit-Reviewer: build bot (Jenkins)