[coreboot-gerrit] Change in coreboot[master]: rockchip: rk3399: add mipi driver
Anonymous Coward (Code Review)
gerrit at coreboot.org
Thu Apr 27 03:51:09 CEST 2017
nickey.yang at rock-chips.com has uploaded a new change for review. ( https://review.coreboot.org/19475 )
Change subject: rockchip: rk3399: add mipi driver
......................................................................
rockchip: rk3399: add mipi driver
This patch configures clock for mipi and then
add mipi driver for support innolux-p079zca
mipi panel in rk3399 scarlet.
Change-Id: I72fdf8a8a60df8b19faa9a30d34829bdae71889d
Signed-off-by: Nickey Yang <nickey.yang at rock-chips.com>
---
M src/soc/rockchip/common/include/soc/vop.h
M src/soc/rockchip/common/vop.c
M src/soc/rockchip/rk3399/Makefile.inc
M src/soc/rockchip/rk3399/chip.h
M src/soc/rockchip/rk3399/clock.c
M src/soc/rockchip/rk3399/display.c
M src/soc/rockchip/rk3399/include/soc/addressmap.h
M src/soc/rockchip/rk3399/include/soc/clock.h
8 files changed, 71 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/19475/1
diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h
index 98ad082..c5c5425 100644
--- a/src/soc/rockchip/common/include/soc/vop.h
+++ b/src/soc/rockchip/common/include/soc/vop.h
@@ -119,6 +119,7 @@
*/
VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
+ VOP_MODE_MIPI,
VOP_MODE_NONE,
VOP_MODE_AUTO_DETECT,
VOP_MODE_UNKNOWN,
diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c
index 629072e..70d59bd 100644
--- a/src/soc/rockchip/common/vop.c
+++ b/src/soc/rockchip/common/vop.c
@@ -24,7 +24,6 @@
#include <soc/edp.h>
#include <soc/vop.h>
-
static struct rockchip_vop_regs * const vop_regs[] = {
(struct rockchip_vop_regs *)VOP_BIG_BASE,
(struct rockchip_vop_regs *)VOP_LIT_BASE
@@ -109,6 +108,7 @@
u32 vfront_porch = edid->mode.vso;
u32 vsync_len = edid->mode.vspw;
u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
+ u32 dsp_out_mode;
struct rockchip_vop_regs *preg = vop_regs[vop_id];
switch (mode) {
@@ -116,17 +116,25 @@
case VOP_MODE_HDMI:
clrsetbits_le32(&preg->sys_ctrl,
M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
+ dsp_out_mode = 15;
break;
-
+ case VOP_MODE_MIPI:
+ clrsetbits_le32(&preg->sys_ctrl,
+ M_ALL_OUT_EN, V_MIPI_OUT_EN(1));
+ dsp_out_mode = 0;
+ break;
case VOP_MODE_EDP:
default:
clrsetbits_le32(&preg->sys_ctrl,
M_ALL_OUT_EN, V_EDP_OUT_EN(1));
+ dsp_out_mode = 15;
break;
}
+
clrsetbits_le32(&preg->dsp_ctrl0,
- M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
- V_DSP_OUT_MODE(15) |
+ M_DSP_OUT_MODE | M_DSP_VSYNC_POL |
+ M_DSP_HSYNC_POL,
+ V_DSP_OUT_MODE(dsp_out_mode) |
V_DSP_HSYNC_POL(edid->mode.phsync == '+') |
V_DSP_VSYNC_POL(edid->mode.pvsync == '+'));
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 8448ff2..54c5115 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -66,6 +66,7 @@
ramstage-y += clock.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi.c
ramstage-y += ../common/gpio.c
ramstage-y += gpio.c
ramstage-y += ../common/i2c.c
diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h
index 1f9462a..1e92567 100644
--- a/src/soc/rockchip/rk3399/chip.h
+++ b/src/soc/rockchip/rk3399/chip.h
@@ -26,6 +26,16 @@
u32 bl_pwm_to_enable_udelay;
u32 framebuffer_bits_per_pixel;
u32 vop_mode;
+ u32 panel_pixel_clock;
+ u32 panel_refresh;
+ u32 panel_ha;
+ u32 panel_hbl;
+ u32 panel_hso;
+ u32 panel_hspw;
+ u32 panel_va;
+ u32 panel_vbl;
+ u32 panel_vso;
+ u32 panel_vspw;
};
#endif /* __SOC_ROCKCHIP_RK3399_CHIP_H__ */
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index eb413a1..640d386 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -863,3 +863,13 @@
(src_clk_div - 1) <<
CLK_PCLK_EDP_DIV_CON_SHIFT));
}
+
+void rkclk_configure_mipi(void)
+{
+ /* Enable clk_mipidphy_ref and clk_mipidphy_cfg */
+ write32(&cru_ptr->clkgate_con[11],
+ RK_CLRBITS(1 << 14 | 1 << 15));
+ /* Enable pclk_mipi_dsi0 */
+ write32(&cru_ptr->clkgate_con[29],
+ RK_CLRBITS(1 << 1));
+}
diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c
index c7ca891..b281669 100644
--- a/src/soc/rockchip/rk3399/display.c
+++ b/src/soc/rockchip/rk3399/display.c
@@ -31,6 +31,7 @@
#include <soc/gpio.h>
#include <soc/grf.h>
#include <soc/mmu_operations.h>
+#include <soc/mipi.h>
#include <soc/soc.h>
#include <soc/vop.h>
@@ -47,6 +48,20 @@
printk(BIOS_WARNING, "Retrying epd initialization.\n");
}
+static void rk_get_mipi_mode(struct edid *edid, device_t dev)
+{
+ struct soc_rockchip_rk3399_config *conf = dev->chip_info;
+ edid->mode.pixel_clock = conf->panel_pixel_clock;
+ edid->mode.refresh = conf->panel_refresh;
+ edid->mode.ha = conf->panel_ha;
+ edid->mode.hbl = conf->panel_hbl;
+ edid->mode.hso = conf->panel_hso;
+ edid->mode.hspw = conf->panel_hspw;
+ edid->mode.va = conf->panel_va;
+ edid->mode.vbl = conf->panel_vbl;
+ edid->mode.vso = conf->panel_vso;
+ edid->mode.vspw = conf->panel_vspw;
+}
void rk_display_init(device_t dev)
{
struct edid edid;
@@ -94,6 +109,21 @@
case VOP_MODE_HDMI:
printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n");
return;
+ case VOP_MODE_MIPI:
+ printk(BIOS_DEBUG, "Attempting to setup MIPI display.\n");
+
+ rkclk_configure_mipi();
+ rkclk_configure_vop_aclk(vop_id, 200 * MHz);
+
+ /* disable turnrequest turndisable forcetxstop forcerxmode */
+ write32(&rk3399_grf->soc_con22, RK_CLRBITS(0xffff));
+ /* select mipi-dsi0 signal from vop0 */
+ write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 0));
+
+ rk_get_mipi_mode(&edid, dev);
+ rk_mipi_init(&edid);
+ detected_mode = VOP_MODE_MIPI;
+ break;
default:
printk(BIOS_WARNING, "Cannot read any EDID info, aborting.\n");
return;
@@ -115,6 +145,10 @@
case VOP_MODE_HDMI:
/* should not be here before HDMI supported */
return;
+ case VOP_MODE_MIPI:
+ rk_mipi_prepare(&edid);
+ mainboard_power_on_backlight();
+ break;
case VOP_MODE_EDP:
default:
/* will enable edp in depthcharge */
@@ -127,5 +161,6 @@
}
set_vbe_mode_info_valid(&edid, (uintptr_t)0);
+
return;
}
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index 1762a8d..7a365ad 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -59,6 +59,7 @@
#define SARADC_BASE 0xff100000
#define RK_PWM_BASE 0xff420000
#define EDP_BASE 0xff970000
+#define MIPI_BASE 0xff960000
#define VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */
#define VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index 3047f73..37a4c09 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -120,5 +120,6 @@
int rkclk_was_watchdog_reset(void);
uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
void rkclk_configure_edp(unsigned int hz);
+void rkclk_configure_mipi(void);
#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I72fdf8a8a60df8b19faa9a30d34829bdae71889d
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: nickey.yang at rock-chips.com
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