[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common smbus code

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/19372 )

Change subject: soc/intel/common/block: Add Intel common smbus code
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Patch Set 4:

(2 comments)

https://review.coreboot.org/#/c/19372/4/src/soc/intel/common/block/smbus/smbus.c
File src/soc/intel/common/block/smbus/smbus.c:

PS4, Line 23: #include <soc/ramstage.h>
you need this for soc_pci_ops? all the IPs which use  will have to include this SOC file. Can we somehow avoid this?
Hypothetical: what if I create a SoC and I pick this IP and I don't want to have a ramstage.h


PS4, Line 95: soc_pci_ops
soc_pci_ops in both APL and SKL is only updating .set_subsystem and both of them have the same implementation.

it is very similar to the function pci_dev_set_subsystem which is in src/device/pci_device.c, can we just extend this function and use it to define a pci_ops in this same file i.e

static struct pci_operations pci_ops = {                                        
        .set_subsystem = &pci_dev_set_subsystem                                 
};


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Gerrit-MessageType: comment
Gerrit-Change-Id: I936143a334c31937d557c6828e5876d35b133567
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
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