[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Set xtal bypass

[Naresh Solanki (Code Review)]

Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/19442 )

Change subject: soc/intel/skylake: Set xtal bypass
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Patch Set 2:

(5 comments)

https://review.coreboot.org/#/c/19442/2/src/soc/intel/skylake/chip.h
File src/soc/intel/skylake/chip.h:

Line 472: 	/* Enable xtal bypass for low power idle */
> This is disabling the gating for s0ix. If so, please indicate it as such. A
xtal bypass bit has its significance w.r.t. low power idle.
Yes it can be linked to single config s0ix_enable. Even I feel its better way.
We do not have FSP UPD to do the same hence setting it in finalize.c


https://review.coreboot.org/#/c/19442/2/src/soc/intel/skylake/finalize.c
File src/soc/intel/skylake/finalize.c:

PS2, Line 91: 	volatile void *pwr_base;
> There is no reason to decorate this variable with volatile.
Right. Will use pmcbase.


PS2, Line 150: config->xtal_bypass
> also can't relate xtal programming with s0ix_enable itself? do xtal bypass 
xtal bypass is related to low power idle i.e., s0ix (SLP_S0_L assertions)


PS2, Line 151: pwr_base
> PWRMBASE is the define for 0x48.
Agree. Will fix that.


PS2, Line 152:  
> one space extra
Oh yes. Will fix it.


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Gerrit-MessageType: comment
Gerrit-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Gerrit-PatchSet: 2
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