[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Update ODT config

[Kane Chen (Code Review)]

Kane Chen has posted comments on this change. ( https://review.coreboot.org/19397 )

Change subject: soc/intel/apollolake: Update ODT config
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Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/19397/3/src/soc/intel/apollolake/include/soc/meminit.h
File src/soc/intel/apollolake/include/soc/meminit.h:

Line 76: 	LP4_CAODT_A_B_HIGH_LOW = 0,   /* default */
> It's bit 1 (not 0) which is holding the CA odt setting:
Hi Aaron,
I went through the MRC code, I think we need set bit 1 for Ch0~Ch3.
See /BXTP/Source/MmrcHooks.c :4745

I guess the odt config description in FSP header for ch1, ch2, ch3 miss the definition of bit 1.

ODMs also verified the stress test issue with Ch0_OdtConfig ~ Ch3_OdtConfig = 2 setting, the result is positive

I'm double checking with FSP/MRC owner on the odt description for each channel
sorry for the inconvenience.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
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