[coreboot-gerrit] Change in coreboot[master]: amd/pi/hudson: Add TPM decode to SPI function

[Marc Jones (Code Review)]

Marc Jones has submitted this change and it was merged. ( https://review.coreboot.org/19402 )

Change subject: amd/pi/hudson: Add TPM decode to SPI function
......................................................................


amd/pi/hudson: Add TPM decode to SPI function

Add a function to send the TPM decode to the SPI interface.
Enables use of SPI TPMs on Hudson mainboards.

Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Signed-off-by: Marc Jones <marcj303 at gmail.com>
Reviewed-on: https://review.coreboot.org/19402
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/hudson.h
M src/southbridge/amd/pi/hudson/lpc.c
3 files changed, 16 insertions(+), 4 deletions(-)

Approvals:
  Stefan Reinauer: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 5f3f0ee..b5e753d 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -327,4 +327,13 @@
 					& ~SPI_READ_MODE_MASK) | mode);
 }
 
+void hudson_tpm_decode_spi(void)
+{
+	device_t dev = PCI_DEV(0, 0x14, 3);	/* LPC device */
+
+	u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase
+							| ROUTE_TPM_2_SPI);
+}
+
 #endif
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 6b6343b..baed2c3 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -69,6 +69,7 @@
 #define REV_HUDSON_A12			0x12
 
 #define SPIROM_BASE_ADDRESS_REGISTER	0xA0
+#define   ROUTE_TPM_2_SPI		BIT(3)
 #define   SPI_ROM_ENABLE		0x02
 #define   SPI_BASE_ADDRESS		0xFEC10000
 
@@ -188,8 +189,7 @@
 void hudson_set_readspeed(u16 norm, u16 fast);
 void lpc_wideio_512_window(uint16_t base);
 void lpc_wideio_16_window(uint16_t base);
-
-
+void hudson_tpm_decode_spi(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #if IS_ENABLED(CONFIG_HUDSON_UART)
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index d73979c..60a1b88 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -126,10 +126,13 @@
 static void hudson_lpc_set_resources(struct device *dev)
 {
 	struct resource *res;
+	u32 spi_enable_bits;
 
-	/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
+	/* Special case. The SpiRomEnable and other enables should STAY set. */
 	res = find_resource(dev, 2);
-	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
+	spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
+	spi_enable_bits &= 0xF;
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits);
 
 	pci_dev_set_resources(dev);
 }

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer at coreboot.org>
Gerrit-Reviewer: build bot (Jenkins)