[coreboot-gerrit] Change in coreboot[master]: vendorcode/amd/pi: Clarify CAR disable

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/19269 )

Change subject: vendorcode/amd/pi: Clarify CAR disable
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Patch Set 2:

(1 comment)

Had this comment stuck in draft.  I'm OK with the change, but I don't want to speak for Aaron.

https://review.coreboot.org/#/c/19269/2/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
File src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc:

Line 411: *   This CPU resume path doesn't use CAR, but be careful if porting to
> Marshall? Do we have proof of concept of S3 on Stoney already?
No, not yet.  I suspect the firmware will have some involvement, i.e. I don't want to rule it out yet.

Perhaps we should have this statement be t.b.d.  From the PSP spec:

 Under secure mode the PSP firmware restores the memory during resume.  Hence, the DRAM is already available when the x86 cores come out of reset on resume.  The availability of DRAM provides an opportunity to optimize the BIOS resume path.  For example, there is no need to perform Cache as RAM initialization...

I'm starting to think "secure mode" is hardware-validated-boot (the spec is a little ambiguous).  Also a bit interesting, the spec says the CRB UEFI doesn't do the optimization above.

> ...x86 would wakeup into postcar after...

I suspect we'd still need to do vboot stuff, regardless.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I1265ed3d1bdf4b22f1a56f68bc53e18cfadc44b2
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
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