[coreboot-gerrit] Change in coreboot[master]: amd/pi/hudson: Add LPC IO decode enable function

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/19160 )

Change subject: amd/pi/hudson: Add LPC IO decode enable function
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Patch Set 12:

(4 comments)

https://review.coreboot.org/#/c/19160/12/src/southbridge/amd/pi/hudson/early_setup.c
File src/southbridge/amd/pi/hudson/early_setup.c:

PS12, Line 190:  = 0
> Aaron earlier mentioned getting rid of this.
Done


Line 200: 		pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp);
> All PIs upto CarrizoPI seem to use WIDEIO0 for SioPmeBaseAddress unconditio
I can't confirm since it depends on when you call this .This code takes care not to overwrite anything. It is called very early on Kahlee, but could be called later as needed on another mainboard.


Line 220: 	lpc_wideio_window(base, 512);
> Alignment check on base?
Done


Line 225: 	lpc_wideio_window(base, 16);
> Alignment check on base?
Done


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Gerrit-MessageType: comment
Gerrit-Change-Id: I2bed3a99180188101e00b4431d634227e488cbda
Gerrit-PatchSet: 12
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
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