[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Set xtal bypass

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded a new change for review. ( https://review.coreboot.org/19442 )

Change subject: soc/intel/skylake: Set xtal bypass
......................................................................

soc/intel/skylake: Set xtal bypass

Some application like Wake On Voice requires xtal to
be active during low power idle.
Hence add config option to bypass xtal gating requiredment
for low power idle.

Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pmc.h
3 files changed, 14 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/19442/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index cd461d4..aeb772a 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -468,6 +468,8 @@
 
 	/* Enable SGX feature */
 	u8 sgx_enable;
+
+	u8 xtal_bypass;
 };
 
 typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index f489e4b..e8e373e 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -88,6 +88,7 @@
 {
 	device_t dev;
 	uint32_t reg32, hsfs;
+	volatile void *pwr_base;
 	void *spibar = get_spi_bar();
 	u16 tcobase;
 	u16 tcocnt;
@@ -143,6 +144,15 @@
 		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
 	}
 
+	/*
+	 * Disable XTAL shutdown qualification for low power idle.
+	 */
+	if (config->xtal_bypass) {
+		pwr_base = (volatile void *)pci_read_config32(PCH_DEV_PMC, 0x48);
+		reg32 = read32(pwr_base + CIR31C );
+		reg32 |= XTALSDQDIS;
+		write32(pwr_base + CIR31C, reg32);
+	}
 	/* we should disable Heci1 based on the devicetree policy */
 	if (config->HeciEnabled == 0)
 		pch_disable_heci();
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 10ea6ae..fc277cb 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -98,5 +98,6 @@
 #define  GPE0_DW2_SHIFT		8
 #define GBLRST_CAUSE0		0x124
 #define GBLRST_CAUSE1		0x128
-
+#define CIR31C			0x31c
+#define	 XTALSDQDIS		(1 << 22)
 #endif

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Rajat Jain <rajatja at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park at intel.corp-partner.google.com>