[coreboot-gerrit] Change in coreboot[master]: google/fizz: Configure memory

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19205 )

Change subject: google/fizz: Configure memory
......................................................................


google/fizz: Configure memory

Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.

BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
     We are currently working on bringup and have no
     hardware to test on yet.

Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Signed-off-by: Shelley Chen <shchen at chromium.org>
Reviewed-on: https://review.coreboot.org/19205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/romstage.c
2 files changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified



diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 377a13c..2d2e6b7 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -13,6 +13,7 @@
 	select MAINBOARD_USES_FSP2_0
 	select NO_FADT_8042
 	select SOC_INTEL_KABYLAKE
+	select GENERIC_SPD_BIN
 
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -38,4 +39,12 @@
 config MAX_CPUS
 	int
 	default 8
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
 endif
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index 8bcfcd3..be1d552 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -15,6 +15,7 @@
 
 #include <soc/romstage.h>
 #include <string.h>
+#include <spd_bin.h>
 
 #include <fsp/soc_binding.h>
 
@@ -28,4 +29,14 @@
 
 	memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
 	memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
+
+	/* Read spd block to get memory config */
+	struct spd_block blk;
+	mem_cfg->DqPinsInterleaved = 1;
+	get_spd_smbus(&blk);
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+
+	dump_spd_info(&blk);
 }

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: build bot (Jenkins)