[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common FAST_SPI code
Furquan Shaikh (Code Review)
gerrit at coreboot.org
Fri Apr 21 09:17:18 CEST 2017
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/18557 )
Change subject: soc/intel/common/block: Add Intel common FAST_SPI code
......................................................................
Patch Set 28:
(11 comments)
https://review.coreboot.org/#/c/18557/25/src/soc/intel/common/block/fast_spi/fast_spi.c
File src/soc/intel/common/block/fast_spi/fast_spi.c:
Line 360
> As I understood from your comment, you are saying that, in spi-generic.h, t
Yeah, I am planning to push a CL to add flash_probe to the spi_ctrlr structure. I believe what you can do is add
struct spi_flash *fast_spi_flash_programmer_probe(struct spi_slave *dev, int force)
which is called from within spi_flash_programmer_probe like this:
struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force)
{
return fast_spi_flash_programmer_probe(...);
}
https://review.coreboot.org/#/c/18557/28/src/soc/intel/common/block/fast_spi/fast_spi.c
File src/soc/intel/common/block/fast_spi/fast_spi.c:
PS28, Line 16: #include <arch/early_variables.h>
Is this required?
PS28, Line 38: bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
Should we assert if bar is 0? To make sure it is set by SoC in early stages?
PS28, Line 49: fast_spi_flash_init
Seems odd that one function in this has _flash_ in the name? Should this be renamed fast_spi_init() instead?
PS28, Line 66: /*
: * Set FAST_SPIBAR BIOS Control BILD bit.
: */
: void fast_spi_set_bios_interface_lock_down(void)
: {
: device_t dev = PCH_DEV_SPI;
: uintptr_t bc_bild;
:
: bc_bild = pci_read_config32(dev, SPIBAR_BIOS_CONTROL);
: bc_bild |= SPIBAR_BIOS_CONTROL_BILD;
: pci_write_config32(dev, SPIBAR_BIOS_CONTROL, bc_bild);
: }
:
: /*
: * Set FAST_SPIBAR BIOS Control LE bit.
: */
: void fast_spi_set_lock_enable(void)
: {
: device_t dev = PCH_DEV_SPI;
: uint8_t bc_le;
:
: bc_le = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
: bc_le |= SPIBAR_BIOS_CONTROL_LOCK_ENABLE;
: pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_le);
: }
:
: /*
: * Set FAST_SPIBAR BIOS Control EISS bit.
: */
: void fast_spi_set_eiss(void)
: {
: device_t dev = PCH_DEV_SPI;
: uint8_t bc_eiss;
:
: bc_eiss = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
: bc_eiss |= SPIBAR_BIOS_CONTROL_EISS;
: pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_eiss);
: }
Can we have one common function:
void fast_spi_set_bios_cntl(uint8_t bios_cntl_bit)
{
device_t dev = PCH_DEV_SPI;
uint8_t bios_cntl;
assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL) | bios_cntl_bit;
pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
}
void fast_spi_set_eiss(void)
{
fast_spi_set_bios_cntl(SPIBAR_BIOS_CONTROL_EISS);
}
void fast_spi_set_lock_enable(void)
{
fast_spi_set_bios_cntl(SPIBAR_BIOS_CONTROL_LOCK_ENABLE);
}
void fast_spi_set_bios_interface_lock_down(void)
{
fast_spi_set_bios_cntl(SPIBAR_BIOS_CONTROL_BILD);
}
PS28, Line 141: ssl |= SPIBAR_RESET_LOCK_DISABLE;
This doesn't look right. Shouldn't this be something like:
ssl &= ~SPIBAR_RESET_LOCK_ENABLE;
https://review.coreboot.org/#/c/18557/28/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
PS28, Line 53: uint32_t bar;
:
: /* FIXME: use device definition */
: ctx->pci_dev = PCH_DEV_SPI;
:
: bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0);
: ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
Can't we use fast_spi_get_bar();
PS28, Line 86: SFPD
SFDP
PS28, Line 101: static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const void *data,
: size_t len)
: {
: len = min(len, SPIBAR_FDATA_FIFO_SIZE);
:
: /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
: memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
: }
:
: /* Drain FDATAn FIFO after a read transaction populates data. */
: static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *dest,
: size_t len)
: {
: len = min(len, SPIBAR_FDATA_FIFO_SIZE);
:
: /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
: memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
: }
Shouldn't this return len so that the caller knows if less than requested bytes were filled/drained?
PS28, Line 147: ,
space after ,
PS28, Line 357: fast_spi_read_wpsr
fast_spi_flash_read_wpsr
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Gerrit-MessageType: comment
Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Gerrit-PatchSet: 28
Gerrit-Project: coreboot
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