[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Align CA ODT settings

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded a new change for review. ( https://review.coreboot.org/19397 )

Change subject: soc/intel/apollolake: Align CA ODT settings
......................................................................

soc/intel/apollolake: Align CA ODT settings

Align CA ODT settings to match HW strappings for LPDDR4.

BUG=chrome-os-partner:37490798
BRANCH=None
TEST=BAT test, warm, reboot, S3 cycle test

Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/soc/intel/apollolake/meminit.c
1 file changed, 4 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19397/1

diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 9546c19..c618a9d 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -74,10 +74,10 @@
 	cfg->Ch3_Option = 0x3;
 
 	/* Weak on-die termination. */
-	cfg->Ch0_OdtConfig = 0;
-	cfg->Ch1_OdtConfig = 0;
-	cfg->Ch2_OdtConfig = 0;
-	cfg->Ch3_OdtConfig = 0;
+	cfg->Ch0_OdtConfig = 2;
+	cfg->Ch1_OdtConfig = 2;
+	cfg->Ch2_OdtConfig = 2;
+	cfg->Ch3_OdtConfig = 2;
 }
 
 void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>