[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: use postcar stage for fsp 2.0

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19335 )

Change subject: soc/intel/skylake: use postcar stage for fsp 2.0
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Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/19335/3/src/soc/intel/skylake/Makefile.inc
File src/soc/intel/skylake/Makefile.inc:

Line 109: 
You will need:
postcar-$(CONFIG_UART_DEBUG) = uart_debug.c


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Gerrit-MessageType: comment
Gerrit-Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: Yes