[coreboot-gerrit] Change in coreboot[master]: soc/intel: [WIP] Create Intel common smi code
Brandon Breitenstein (Code Review)
gerrit at coreboot.org
Thu Apr 20 01:18:17 CEST 2017
Brandon Breitenstein has uploaded a new change for review. ( https://review.coreboot.org/19381 )
Change subject: soc/intel: [WIP] Create Intel common smi code
......................................................................
soc/intel: [WIP] Create Intel common smi code
Much of the code for smi is common between all platforms. This patch
creates a common file under soc/intel/common/smi.c which contains the
common code. Already tested working with APL but still in progress for
the SKL code to get it properly working with the new common SMI code
Change-Id: Idb4335a05506e0d214b74d813bbeb2bf9b609f55
Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/common/Makefile.inc
A src/soc/intel/common/smi.c
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/include/soc/pm.h
6 files changed, 120 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/19381/1
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 1e6aafd..9fe3149 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -75,7 +75,6 @@
ramstage-y += pmutil.c
ramstage-y += pmc.c
ramstage-y += reset.c
-ramstage-y += smi.c
ramstage-y += sram.c
ramstage-y += spi.c
ramstage-y += xdci.c
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index f754541..35b8cd3 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -81,6 +81,8 @@
#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */
#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */
#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */
+/* Make enable_smi params a variable since it differs by platform */
+#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | BGL_SMI_EN | EOS | GPIO_EN)
#define SMI_STS 0x44
/* Bits for SMI status */
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index acfd054..7b8763e 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -34,6 +34,8 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_SMI) += smi.c
+
smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
diff --git a/src/soc/intel/common/smi.c b/src/soc/intel/common/smi.c
new file mode 100644
index 0000000..f2b5576
--- /dev/null
+++ b/src/soc/intel/common/smi.c
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <string.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+
+void smi_southbridge_smm_clear_state(void)
+{
+ u32 smi_en;
+
+ printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
+ printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);
+
+ if (get_smi_en() & APMC_EN) {
+ printk(BIOS_INFO, "SMI# handler already enabled?\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "Done\n");
+
+ /* Dump and clear status registers */
+ clear_smi_status();
+ clear_pm1_status();
+ clear_tco_status();
+ clear_gpe_status();
+}
+
+void smi_southbridge_smm_enable_smi(void)
+{
+ printk(BIOS_DEBUG, "Enabling SMIs.\n");
+ /* Configure events */
+ enable_pm1(PWRBTN_EN | GBL_EN);
+ disable_gpe(PME_B0_EN);
+
+
+ /* Enable SMI generation: */
+ enable_smi(ENABLE_SMI_PARAMS);
+}
+
+void southbridge_trigger_smi(void)
+{
+ /*
+ * There are several methods of raising a controlled SMI# via
+ * software, among them:
+ * - Writes to io 0xb2 (APMC)
+ * - Writes to the Local Apic ICR with Delivery mode SMI.
+ *
+ * Using the local apic is a bit more tricky. According to
+ * AMD Family 11 Processor BKDG no destination shorthand must be
+ * used.
+ * The whole SMM initialization is quite a bit hardware specific, so
+ * I'm not too worried about the better of the methods at the moment
+ */
+
+ /* raise an SMI interrupt */
+ printk(BIOS_SPEW, " ... raise SMI#\n");
+ outb(0x00, 0xb2);
+}
+
+void southbridge_clear_smi_status(void)
+{
+ /* Clear SMI status */
+ clear_smi_status();
+
+ /* Clear PM1 status */
+ clear_pm1_status();
+
+ /* Set EOS bit so other SMIs can occur. */
+ enable_smi(EOS);
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+ /*
+ * Issue SMI to set the gnvs pointer in SMM.
+ * tcg and smi1 are unused.
+ *
+ * EAX = APM_CNT_GNVS_UPDATE
+ * EBX = gnvs pointer
+ * EDX = APM_CNT
+ */
+ asm volatile (
+ "outb %%al, %%dx\n\t"
+ : /* ignore result */
+ : "a" (APM_CNT_GNVS_UPDATE),
+ "b" ((u32)gnvs),
+ "d" (APM_CNT)
+ );
+}
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 2ef4bba..9718d23 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -83,7 +83,6 @@
ramstage-y += sgx.c
ramstage-y += smbus.c
ramstage-y += smbus_common.c
-ramstage-y += smi.c
ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 7112c77..e425cc8 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -135,6 +135,9 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
+/* Make enable_smi flags a single value */
+#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
--
To view, visit https://review.coreboot.org/19381
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Idb4335a05506e0d214b74d813bbeb2bf9b609f55
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein at intel.com>
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