[coreboot-gerrit] Change in coreboot[master]: nb/amd/amdk8: Link incoherent_ht.c
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed Apr 19 16:58:41 CEST 2017
Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19368 )
Change subject: nb/amd/amdk8: Link incoherent_ht.c
......................................................................
nb/amd/amdk8: Link incoherent_ht.c
This moves get_sbdn declartion from romstage.c files to southbridge
code.
Change-Id: I58fa35ba9c96d00a8852d807b679e772f8286f85
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/amd/dbm690t/romstage.c
M src/mainboard/amd/mahogany/romstage.c
M src/mainboard/amd/pistachio/romstage.c
M src/mainboard/amd/serengeti_cheetah/romstage.c
M src/mainboard/asrock/939a785gmh/romstage.c
M src/mainboard/asus/a8n_e/romstage.c
M src/mainboard/asus/a8v-e_deluxe/romstage.c
M src/mainboard/asus/a8v-e_se/romstage.c
M src/mainboard/asus/k8v-x/romstage.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kfsn4-dre_k8/romstage.c
M src/mainboard/asus/m2n-e/romstage.c
M src/mainboard/asus/m2v-mx_se/romstage.c
M src/mainboard/asus/m2v/romstage.c
M src/mainboard/broadcom/blast/romstage.c
M src/mainboard/gigabyte/ga_2761gxdk/romstage.c
M src/mainboard/gigabyte/m57sli/romstage.c
M src/mainboard/hp/dl145_g1/romstage.c
M src/mainboard/hp/dl145_g3/romstage.c
M src/mainboard/iwill/dk8_htx/romstage.c
M src/mainboard/kontron/kt690/romstage.c
M src/mainboard/msi/ms7135/romstage.c
M src/mainboard/msi/ms7260/romstage.c
M src/mainboard/msi/ms9185/romstage.c
M src/mainboard/msi/ms9282/romstage.c
M src/mainboard/nvidia/l1_2pvv/romstage.c
M src/mainboard/siemens/sitemp_g1p1/romstage.c
M src/mainboard/sunw/ultra40/romstage.c
M src/mainboard/sunw/ultra40m2/romstage.c
M src/mainboard/supermicro/h8dme/romstage.c
M src/mainboard/supermicro/h8dmr/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/technexion/tim5690/romstage.c
M src/mainboard/technexion/tim8690/romstage.c
M src/mainboard/tyan/s2912/romstage.c
M src/mainboard/tyan/s2912_fam10/romstage.c
M src/mainboard/winent/mb6047/romstage.c
M src/northbridge/amd/amdk8/Makefile.inc
M src/northbridge/amd/amdk8/amdk8.h
M src/northbridge/amd/amdk8/incoherent_ht.c
M src/southbridge/amd/amd8111/amd8111.h
M src/southbridge/amd/sb600/early_setup.c
M src/southbridge/amd/sb600/sb600.h
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/mcp55/early_ctrl.c
M src/southbridge/nvidia/mcp55/mcp55.h
51 files changed, 72 insertions(+), 292 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/19368/1
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index b4a3d12..3b5ce6b 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -45,7 +45,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index a8e54d5..c99ea63 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -34,8 +34,6 @@
#include <southbridge/amd/sb700/smbus.h>
#include <northbridge/amd/amdk8/f.h>
-unsigned get_sbdn(unsigned bus);
-
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -48,7 +46,6 @@
#include "southbridge/amd/rs780/early_setup.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 2008619..4a5f092 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -41,7 +41,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 73a1e9f..0ab4689 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -34,8 +34,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-unsigned get_sbdn(unsigned bus);
-
static void memreset_setup(void)
{
/* GPIO on amd8111 to enable MEMRST ???? */
@@ -66,7 +64,6 @@
#include "southbridge/amd/amd8111/early_ctrl.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index bd74fde..e71473b 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -38,8 +38,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
-unsigned get_sbdn(unsigned bus);
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -50,7 +48,6 @@
#include "southbridge/amd/rs780/early_setup.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 5a3b1f6..8c8938e 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -33,7 +33,6 @@
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 3601e50..5ac5c0d 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -18,8 +18,6 @@
* GNU General Public License for more details.
*/
-unsigned int get_sbdn(unsigned bus);
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -72,22 +70,12 @@
#include "southbridge/via/k8t890/early_car.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
static void sio_init(void)
{
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index fdb8577..192ccbc 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -18,8 +18,6 @@
* GNU General Public License for more details.
*/
-unsigned int get_sbdn(unsigned bus);
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -72,22 +70,12 @@
#include "southbridge/via/k8t890/early_car.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
static void sio_init(void)
{
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index f1477c3..ea44835 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -18,8 +18,6 @@
* GNU General Public License for more details.
*/
-unsigned int get_sbdn(unsigned bus);
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -70,7 +68,6 @@
#include "southbridge/via/k8t890/early_car.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -78,14 +75,6 @@
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 53ec731..7f1ad56 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -67,20 +67,6 @@
return smbus_read_byte(device, address);
}
-/**
- * @brief Get SouthBridge device number
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
- return (dev >> 15) & 0x1f;
-}
-
/*
* ASUS KFSN4-DRE specific SPD enable/disable magic.
*
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
index d5fdec5..b961fa1 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
@@ -17,8 +17,6 @@
* GNU General Public License for more details.
*/
-unsigned int get_sbdn(unsigned bus);
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -51,7 +49,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -74,14 +71,6 @@
* @param[in] bus target bus number
* @return southbridge device number
*/
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
- return (dev >> 15) & 0x1f;
-}
/*
* ASUS KFSN4-DRE specific SPD enable/disable magic.
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index 915ca84..55f8a56 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -41,19 +41,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) {}
void activate_spd_rom(const struct mem_controller *ctrl) {}
@@ -63,7 +50,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 7864f96..7ba494b 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -18,8 +18,6 @@
* GNU General Public License for more details.
*/
-unsigned int get_sbdn(unsigned bus);
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -55,7 +53,6 @@
#include "southbridge/via/k8t890/early_car.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -95,15 +92,6 @@
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 89948b7..a34358c 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -18,8 +18,6 @@
* GNU General Public License for more details.
*/
-unsigned int get_sbdn(unsigned bus);
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -57,7 +55,6 @@
#include "southbridge/via/k8t890/early_car.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -78,15 +75,6 @@
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
}
struct gpio_init_val {
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index f49f8d3..98576f5 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -7,7 +7,6 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
@@ -21,7 +20,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-unsigned get_sbdn(unsigned bus);
static void memreset_setup(void) { }
void memreset(int controllers, const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 6a18e98..61e67fd 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -52,7 +52,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index d4b6367..0461adc 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -38,19 +38,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -70,7 +57,6 @@
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 7c54a79..bbed002 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -23,8 +23,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-unsigned get_sbdn(unsigned bus);
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -81,7 +79,6 @@
}
#include "southbridge/amd/amd8111/early_ctrl.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "lib/generic_sdram.c"
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 0dcc6e5..297839d 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -44,8 +44,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-unsigned get_sbdn(unsigned bus);
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl)
@@ -64,7 +62,6 @@
#include "southbridge/broadcom/bcm5785/early_setup.c"
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include <spd.h>
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 9d29ae2..edfa564 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -19,8 +19,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-unsigned get_sbdn(unsigned bus);
-
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
@@ -57,7 +55,6 @@
#include "southbridge/amd/amd8111/early_ctrl.c"
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 7769647..43f5fa3 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -46,7 +46,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 08fbdc7..981615f 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -30,7 +30,6 @@
#include <superio/winbond/w83627thg/w83627thg.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 6feddcf..2cb2dbc 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -40,19 +40,6 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) {}
void activate_spd_rom(const struct mem_controller *ctrl) {}
@@ -62,7 +49,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 56eaa6a..d8bd93b 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -42,8 +42,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-unsigned get_sbdn(unsigned bus);
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl)
@@ -62,7 +60,6 @@
#include "southbridge/broadcom/bcm5785/early_setup.c"
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index fd90491..26ae84d 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -41,19 +41,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl)
@@ -71,7 +58,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index b80f4f3..18fea45 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -39,19 +39,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -61,7 +48,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 6ac79d1..c1a11b4 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -61,7 +61,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 1345871..7abdf23 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -9,7 +9,6 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index 44bf851..1cc1dc5 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -38,19 +38,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -60,7 +47,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index d0ab05e..c8c52c8 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -37,19 +37,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl)
@@ -70,7 +57,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index e4ee1c8..9e9452b 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -40,19 +40,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -62,7 +49,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index d457f1b..d8a405c 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -63,17 +63,6 @@
return smbus_read_byte(device, address);
}
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
static void sio_setup(void)
{
uint32_t dword;
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 26f3da7..eff3361 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -69,17 +69,6 @@
return smbus_read_byte(device, address);
}
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
static void sio_setup(void)
{
uint32_t dword;
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 3b4b4fd..5f06af4 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -46,7 +46,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 6030864..bed5aa2 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -47,7 +47,6 @@
}
#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 6a47612..040ca2e 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -39,19 +39,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
void memreset(int controllers, const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -61,7 +48,6 @@
}
#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 4c8c19f..9ea2c75 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -70,17 +70,6 @@
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
static void sio_setup(void)
{
uint32_t dword;
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
index 09de180..b2c86fb 100644
--- a/src/mainboard/winent/mb6047/romstage.c
+++ b/src/mainboard/winent/mb6047/romstage.c
@@ -9,7 +9,6 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <northbridge/amd/amdk8/raminit.h>
#include <delay.h>
diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc
index c6b1ac6..0b4ea9b 100644
--- a/src/northbridge/amd/amdk8/Makefile.inc
+++ b/src/northbridge/amd/amdk8/Makefile.inc
@@ -13,6 +13,7 @@
romstage-y += reset_test.c
romstage-y += coherent_ht.c
+romstage-y += incoherent_ht.c
# Enable this if you want to check the values of the PCI routing registers.
# Call show_all_routes() anywhere amdk8.h is included.
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index e335a98..506d029 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -26,10 +26,19 @@
void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);
int optimize_link_coherent_ht(void);
unsigned int get_nodes(void);
-#if CONFIG_RAMINIT_SYSINFO
+int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid,
+ unsigned int val);
+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)
void setup_coherent_ht_domain(void);
+void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
+ unsigned int offset_unitid, struct sys_info *sysinfo);
+void ht_setup_chains_x(struct sys_info *sysinfo);
+int optimize_link_incoherent_ht(struct sys_info *sysinfo);
#else
int setup_coherent_ht_domain(void);
+int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
+ unsigned int offset_unitid);
+int ht_setup_chains_x(void);
#endif
#endif
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 1f9e9ff..e852754 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -3,10 +3,29 @@
2004.12 yhlu add multi ht chain dynamically support
2005.11 yhlu add let real sb to use small unitid
*/
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
#include <lib.h>
+#include <stdint.h>
+#include "amdk8.h"
+
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AMD8111)
+#include <southbridge/amd/amd8111/amd8111.h>
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB600)
+#include <southbridge/amd/sb600/sb700.h>
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB600)
+#include <southbridge/amd/sb600/sb700.h>
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785)
+#include <southbridge/broadcom/bcm5785/bcm5785.h>
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_CK804)
+#include <southbridge/nvidia/ck804/ck804.h>
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55)
+#include <southbridge/nvidia/mcp55/mcp55.h>
+#endif
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
@@ -283,11 +302,11 @@
}
#if CONFIG_RAMINIT_SYSINFO
-static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
- unsigned offset_unitid, struct sys_info *sysinfo)
+void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
+ unsigned int offset_unitid, struct sys_info *sysinfo)
#else
-static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
- unsigned offset_unitid)
+int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
+ unsigned int offset_unitid)
#endif
{
//even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
@@ -526,7 +545,6 @@
return reset_needed;
}
-#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
@@ -553,7 +571,8 @@
return 0;
}
-static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val)
+int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid,
+ unsigned int val)
{
int reset_needed;
uint8_t i;
@@ -584,7 +603,6 @@
return reset_needed;
}
-#endif
#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
@@ -650,9 +668,9 @@
}
#if CONFIG_RAMINIT_SYSINFO
-static void ht_setup_chains_x(struct sys_info *sysinfo)
+void ht_setup_chains_x(struct sys_info *sysinfo)
#else
-static int ht_setup_chains_x(void)
+int ht_setup_chains_x(void)
#endif
{
uint8_t nodeid;
@@ -788,7 +806,7 @@
}
#if CONFIG_RAMINIT_SYSINFO
-static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
+int optimize_link_incoherent_ht(struct sys_info *sysinfo)
{
// We need to use recorded link pair info to optimize the link
int i;
diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h
index 10df590..e0be202 100644
--- a/src/southbridge/amd/amd8111/amd8111.h
+++ b/src/southbridge/amd/amd8111/amd8111.h
@@ -9,6 +9,7 @@
#ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+unsigned int get_sbdn(unsigned int bus);
#endif
#endif /* AMD8111_H */
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 2445310..fc05a13 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -100,7 +100,7 @@
}
/* what is its usage? */
-static u32 get_sbdn(u32 bus)
+u32 get_sbdn(u32 bus)
{
pci_devfn_t dev;
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 94ee861..7ad1881 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -29,6 +29,8 @@
#define HPET_BASE_ADDRESS 0xfed00000
+u32 get_sbdn(u32 bus);
+
#ifndef __ACPI__
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index f20c1e1..e549e8a 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -30,8 +30,6 @@
#include "sb700.h"
#include "smbus.h"
-u32 get_sbdn(u32 bus);
-
static void pmio_write(u8 reg, u8 value)
{
outb(reg, PM_INDEX);
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 6b34502..ac4d163 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -71,6 +71,7 @@
void sb7xx_51xx_early_setup(void);
void sb7xx_51xx_before_pci_init(void);
uint16_t sb7xx_51xx_decode_last_reset(void);
+u32 get_sbdn(u32 bus);
#else
#include <device/pci.h>
/* allow override in mainboard.c */
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
index 893a46c..c372ab7 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.h
@@ -23,6 +23,7 @@
void bcm5785_enable(device_t dev);
#else
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+unsigned int get_sbdn(unsigned int bus);
#endif
void ldtstop_sb(void);
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index 405211a..3bd57dc 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -33,6 +33,8 @@
#ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+unsigned int get_sbdn(unsigned int bus);
+#else
#endif
#endif
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 689f989..9d20f75 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -20,7 +20,9 @@
#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8)
/* Someone messed up and snuck in some K8-specific code */
-static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */};
+static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */};
+#else
+#include <northbridge/amd/amdk8/amdk8.h>
#endif
static int set_ht_link_ck804(u8 ht_c_num)
@@ -380,3 +382,12 @@
/* The default value for CK804 is good. */
/* Set VFSMAF (VID/FID System Management Action Field) to 2. */
}
+
+unsigned int get_sbdn(unsigned bus)
+{
+ pci_devfn_t dev;
+
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
+ PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
+ return (dev >> 15) & 0x1f;
+}
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 1f80316..0f90646 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <console/console.h>
+#include <device/pci_ids.h>
#include <reset.h>
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8)
#include <northbridge/amd/amdk8/amdk8.h>
@@ -47,3 +48,14 @@
/* The default value for MCP55 is good. */
/* Set VFSMAF (VID/FID System Management Action Field) to 2. */
}
+
+unsigned int get_sbdn(unsigned int bus)
+{
+ pci_devfn_t dev;
+
+ /* Find the device. */
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
+ PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
+
+ return (dev >> 15) & 0x1f;
+}
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index a244b82..9bc31dd 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -40,6 +40,7 @@
int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
unsigned char val);
+unsigned int get_sbdn(unsigned int bus);
#endif
#endif
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I58fa35ba9c96d00a8852d807b679e772f8286f85
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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