[coreboot-gerrit] Change in coreboot[master]: google/oak: support cr50 over i2c on rowan

[Daniel Kurtz (Code Review)]

Daniel Kurtz has uploaded a new change for review. ( https://review.coreboot.org/19364 )

Change subject: google/oak: support cr50 over i2c on rowan
......................................................................

google/oak: support cr50 over i2c on rowan

This patch enables TPM2 using CR50 over i2c for the Rowan board, and
adds an mt8173 specific TPM polling function. The function relies on
the appropriate EINT input configured to trigger the ready status on
the rising edge.

The Cr50 interrupt gpio is also made available for use by depthcharge
via lib_gpios.

Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>

BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and deptcharge are
 configured to use irq flow control when talking to the Cr50 TPM.

Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
---
M src/mainboard/google/oak/Kconfig
M src/mainboard/google/oak/bootblock.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/oak/gpio.h
M src/soc/mediatek/mt8173/Makefile.inc
5 files changed, 28 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/19364/1

diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig
index 28771b8..33b3560 100644
--- a/src/mainboard/google/oak/Kconfig
+++ b/src/mainboard/google/oak/Kconfig
@@ -18,6 +18,11 @@
 
 if BOARD_GOOGLE_OAK_COMMON
 
+config OAK_HAS_TPM2
+	bool "Build for a board revision with a SPI TPM 2.0"
+	default y if BOARD_GOOGLE_ROWAN
+	default n if !BOARD_GOOGLE_ROWAN
+
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select SOC_MEDIATEK_MT8173
@@ -32,6 +37,8 @@
 	select MAINBOARD_HAS_CHROMEOS
 	select RAM_CODE_SUPPORT
 	select SPI_FLASH
+	select MAINBOARD_HAS_I2C_TPM_CR50 if OAK_HAS_TPM2
+	select MAINBOARD_HAS_TPM2 if OAK_HAS_TPM2
 
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -56,7 +63,8 @@
 
 config DRIVER_TPM_I2C_ADDR
 	hex
-	default 0x20
+	default 0x20 if !OAK_HAS_TPM2
+	default 0x50 if OAK_HAS_TPM2
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 04a3a55..c3e3820 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -88,6 +88,9 @@
 	/* Init i2c bus 2 Timing register for TPM */
 	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
 
+	if (IS_ENABLED(CONFIG_OAK_HAS_TPM2))
+		eint_configure(PAD_EINT16, MTK_EINT_D0, MTK_EINT_EDGE_RISING);
+
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
 
 	setup_chromeos_gpios();
diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c
index a581364..ee17861 100644
--- a/src/mainboard/google/oak/chromeos.c
+++ b/src/mainboard/google/oak/chromeos.c
@@ -18,6 +18,7 @@
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
 #include <string.h>
+#include <tpm.h>
 
 #include "gpio.h"
 
@@ -42,6 +43,9 @@
 		{POWER_BUTTON, ACTIVE_HIGH, -1, "power"},
 		{EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"},
 		{EC_IRQ, ACTIVE_LOW, -1, "EC interrupt"},
+#if IS_ENABLED(CONFIG_OAK_HAS_TPM2)
+		{CR50_IRQ, ACTIVE_HIGH, -1, "Cr50 interrupt"},
+#endif
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
@@ -50,3 +54,10 @@
 {
 	return !gpio_get(WRITE_PROTECT);
 }
+
+#if IS_ENABLED(CONFIG_OAK_HAS_TPM2)
+int tis_plat_irq_status(void)
+{
+	return eint_poll(CR50_IRQ);
+}
+#endif
diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h
index 3c0f51a..c4c7b24 100644
--- a/src/mainboard/google/oak/gpio.h
+++ b/src/mainboard/google/oak/gpio.h
@@ -42,6 +42,10 @@
 	EC_IN_RW	= PAD_DAIPCMIN,
 	/* EC AP suspend */
 	EC_SUSPEND_L	= PAD_KPROW1,
+#if IS_ENABLED(CONFIG_OAK_HAS_TPM2)
+	/* Cr50 interrupt */
+	CR50_IRQ	= PAD_EINT16,
+#endif
 };
 
 void setup_chromeos_gpios(void);
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index b79492d..fecd7f1 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -40,6 +40,7 @@
 verstage-y += timer.c
 verstage-y += wdt.c
 verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
+verstage-y += gpio.c
 
 ################################################################################
 

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Daniel Kurtz <djkurtz at google.com>
Gerrit-Reviewer: Daniel Kurtz <djkurtz at chromium.org>
Gerrit-Reviewer: Vadim Bendebury <vbendeb at chromium.org>