[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8173: Add EINT support

[Daniel Kurtz (Code Review)]

Daniel Kurtz has uploaded a new change for review. ( https://review.coreboot.org/19362 )

Change subject: mediatek/mt8173: Add EINT support
......................................................................

mediatek/mt8173: Add EINT support

Add basic support for configuring and polling external interrupts (EINT).

Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>

BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and deptcharge are
 configured to use irq flow control when talking to the Cr50 TPM.

Change-Id: I9d52591661a5a74ec1fd9a081f606f0a08a3a6ab
---
M src/soc/mediatek/mt8173/gpio.c
M src/soc/mediatek/mt8173/include/soc/addressmap.h
M src/soc/mediatek/mt8173/include/soc/gpio.h
3 files changed, 114 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/19362/1

diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c
index e19c769..8459b3f 100644
--- a/src/soc/mediatek/mt8173/gpio.c
+++ b/src/soc/mediatek/mt8173/gpio.c
@@ -25,6 +25,7 @@
 	MAX_GPIO_REG_BITS = 16,
 	MAX_GPIO_MODE_PER_REG = 5,
 	GPIO_MODE_BITS = 3,
+	MAX_EINT_REG_BITS = 32,
 };
 
 enum {
@@ -46,6 +47,12 @@
 {
 	*pos = pin / MAX_GPIO_MODE_PER_REG;
 	*bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
+}
+
+static void pos_bit_calc_for_eint(u32 pin, u32 *pos, u32 *bit)
+{
+	*pos = pin / MAX_EINT_REG_BITS;
+	*bit = pin % MAX_EINT_REG_BITS;
 }
 
 static s32 gpio_set_dir(u32 pin, u32 dir)
@@ -175,3 +182,62 @@
 	gpio_set_dir(gpio, GPIO_DIRECTION_OUT);
 	gpio_set_mode(gpio, GPIO_MODE);
 }
+
+int eint_poll(gpio_t gpio)
+{
+	u32 pos;
+	u32 bit;
+	u32 status;
+
+	assert(gpio <= MAX_8173_GPIO);
+
+	pos_bit_calc_for_eint(gpio, &pos, &bit);
+
+	status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1;
+
+	if (status)
+		write32(&mt8173_eint->ack.regs[pos], 1 << bit);
+
+	return status;
+}
+
+void eint_configure(gpio_t gpio, enum eint_domain domain,
+		    enum eint_sense_polarity type)
+{
+	u32 pos;
+	u32 bit, mask;
+
+	assert(gpio <= MAX_8173_GPIO);
+
+	pos_bit_calc_for_eint(gpio, &pos, &bit);
+	mask = 1 << bit;
+
+	/* Make it an input first. */
+	gpio_input_pullup(gpio);
+
+	if (domain == MTK_EINT_D0)
+		write32(&mt8173_eint->d0en[pos], mask);
+	else
+		write32(&mt8173_eint->d1en[pos], mask);
+
+	switch (type) {
+	case MTK_EINT_EDGE_FALLING:
+		write32(&mt8173_eint->sens_clr.regs[pos], mask);
+		write32(&mt8173_eint->pol_clr.regs[pos], mask);
+		break;
+	case MTK_EINT_EDGE_RISING:
+		write32(&mt8173_eint->sens_clr.regs[pos], mask);
+		write32(&mt8173_eint->pol_set.regs[pos], mask);
+		break;
+	case MTK_EINT_LEVEL_LOW:
+		write32(&mt8173_eint->sens_set.regs[pos], mask);
+		write32(&mt8173_eint->pol_clr.regs[pos], mask);
+		break;
+	case MTK_EINT_LEVEL_HIGH:
+		write32(&mt8173_eint->sens_set.regs[pos], mask);
+		write32(&mt8173_eint->pol_set.regs[pos], mask);
+		break;
+	}
+
+	write32(&mt8173_eint->mask_clr.regs[pos], mask);
+}
diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h
index 3b67c09..cc1b39d 100644
--- a/src/soc/mediatek/mt8173/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h
@@ -34,6 +34,7 @@
 	SPM_BASE		= IO_PHYS + 0x6000,
 	RGU_BASE		= IO_PHYS + 0x7000,
 	GPT_BASE		= IO_PHYS + 0x8000,
+	EINT_BASE		= IO_PHYS + 0xB000,
 	PMIC_WRAP_BASE		= IO_PHYS + 0xD000,
 	CHA_DDRPHY_BASE		= IO_PHYS + 0xF000,
 	CHB_DRAMCAO_BASE	= IO_PHYS + 0x11000,
diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h
index 3968d04..4ce3540 100644
--- a/src/soc/mediatek/mt8173/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8173/include/soc/gpio.h
@@ -87,4 +87,51 @@
 void gpio_set_mode(gpio_t gpio, int mode);
 void gpio_init(enum external_power);
 
+enum eint_domain {
+	MTK_EINT_D0,
+	MTK_EINT_D1,
+};
+
+enum eint_sense_polarity {
+	MTK_EINT_EDGE_FALLING,
+	MTK_EINT_EDGE_RISING,
+	MTK_EINT_LEVEL_LOW,
+	MTK_EINT_LEVEL_HIGH,
+};
+
+struct eint_section {
+	uint32_t	regs[7];
+	uint32_t	align1[9];
+};
+
+struct eint_regs {
+	struct eint_section sta;
+	struct eint_section ack;
+	struct eint_section mask;
+	struct eint_section mask_set;
+	struct eint_section mask_clr;
+	struct eint_section sens;
+	struct eint_section sens_set;
+	struct eint_section sens_clr;
+	struct eint_section soft;
+	struct eint_section soft_set;
+	struct eint_section soft_clr;
+	struct eint_section rsv00;
+	struct eint_section pol;
+	struct eint_section pol_set;
+	struct eint_section pol_clr;
+	struct eint_section rsv01;
+	uint32_t	    d0en[7];
+	uint32_t	    rsv02;
+	uint32_t	    d1en[7];
+};
+
+check_member(eint_regs, d1en, 0x420);
+
+static struct eint_regs *const mt8173_eint = (void *)(EINT_BASE);
+
+int eint_poll(gpio_t gpio);
+void eint_configure(gpio_t gpio, enum eint_domain domain,
+		    enum eint_sense_polarity type);
+
 #endif /* SOC_MEDIATEK_MT8173_GPIO_H */

-- 
To view, visit https://review.coreboot.org/19362
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I9d52591661a5a74ec1fd9a081f606f0a08a3a6ab
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Daniel Kurtz <djkurtz at google.com>
Gerrit-Reviewer: Daniel Kurtz <djkurtz at chromium.org>