[coreboot-gerrit] Change in coreboot[master]: [WIP]nb/amd/amdk8: Link reset_test.c

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19360 )

Change subject: [WIP]nb/amd/amdk8: Link reset_test.c
......................................................................

[WIP]nb/amd/amdk8: Link reset_test.c

Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/gigabyte/m57sli/romstage.c
M src/northbridge/amd/amdk8/Makefile.inc
M src/northbridge/amd/amdk8/amdk8.h
M src/northbridge/amd/amdk8/reset_test.c
4 files changed, 12 insertions(+), 8 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/19360/1

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index c58b526..cdd6d43 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -30,7 +30,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include <cpu/x86/bist.h>
diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc
index fb2aca5..90c36a5 100644
--- a/src/northbridge/amd/amdk8/Makefile.inc
+++ b/src/northbridge/amd/amdk8/Makefile.inc
@@ -9,6 +9,7 @@
 ifeq ($(CONFIG_K8_REV_F_SUPPORT),y)
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += exit_from_self.c
 romstage-y += raminit_f.c
+romstage-y += reset_test.c
 endif
 
 # Enable this if you want to check the values of the PCI routing registers.
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index 8c472ae..c3474d7 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -11,12 +11,19 @@
 	#include "pre_f.h"
 #endif
 
+#define HTIC_ColdR_Detect  (1<<4)
+#define HTIC_BIOSR_Detect  (1<<5)
+#define HTIC_INIT_Detect   (1<<6)
+
 #ifdef __PRE_RAM__
 void showallroutes(int level, pci_devfn_t dev);
 void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base);
 void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);
 #endif
 
+void set_bios_reset(void);
+void distinguish_cpu_resets(unsigned int nodeid);
+
 void cpus_ready_for_init(void);
 
 #endif /* AMDK8_H */
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index f998c48..4ae4404 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -1,10 +1,8 @@
+#include <arch/io.h>
+#include <console/console.h>
 #include <stdint.h>
 #include <cpu/x86/lapic.h>
-#include "raminit.h"
-
-#define HTIC_ColdR_Detect  (1<<4)
-#define HTIC_BIOSR_Detect  (1<<5)
-#define HTIC_INIT_Detect   (1<<6)
+#include "amdk8.h"
 
 static inline int cpu_init_detected(unsigned nodeid)
 {
@@ -33,7 +31,7 @@
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static inline void distinguish_cpu_resets(unsigned nodeid)
+void distinguish_cpu_resets(unsigned int nodeid)
 {
 	u32 htic;
 	pci_devfn_t device;
@@ -43,7 +41,6 @@
 	pci_io_write_config32(device, HT_INIT_CONTROL, htic);
 }
 
-void set_bios_reset(void);
 void set_bios_reset(void)
 {
 	u32 htic;

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>