[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common FAST_SPI code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18557 )

Change subject: soc/intel/common/block: Add Intel common FAST_SPI code
......................................................................


Patch Set 24:

(11 comments)

https://review.coreboot.org/#/c/18557/24/src/soc/intel/common/block/fast_spi/fast_spi.c
File src/soc/intel/common/block/fast_spi/fast_spi.c:

PS24, Line 117: /* Write to register in FAST_SPI flash controller. 'reg' is the register offset. */
              : static void _fast_spi_flash_ctrlr_reg_write(struct fast_spi_flash_ctx *ctx, uint16_t reg,
              : 				       uint32_t val)
>80


PS24, Line 157: static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *dest, size_t len)
>80


PS24, Line 166: static void start_hwseq_xfer(struct fast_spi_flash_ctx *ctx, uint32_t hsfsts_cycle,
              : 				 uint32_t flash_addr, size_t len)
-same


PS24, Line 198: 	/* TODO: set up timer and abort on timeout */
still this TODO valid?


PS24, Line 278: static int nuclear_fast_spi_flash_read(const struct spi_flash *flash, uint32_t addr,
              : 				size_t len, void *buf)
>80


PS24, Line 305: static int nuclear_fast_spi_flash_write(const struct spi_flash *flash, uint32_t addr,
              : 				size_t len, const void *buf)
>80


PS24, Line 331: static int nuclear_fast_spi_flash_status(const struct spi_flash *flash, uint8_t *reg)
>80


https://review.coreboot.org/#/c/18557/24/src/soc/intel/common/block/fast_spi/fast_spi_def.h
File src/soc/intel/common/block/fast_spi/fast_spi_def.h:

PS24, Line 25: 	
remove one tab


PS24, Line 52: /* Bit definitions for BFPREG (0x00) register */
             : #define SPIBAR_BFPREG_PRB_MASK		(0x7fff)
             : #define SPIBAR_BFPREG_PRL_SHIFT	(16)
             : #define SPIBAR_BFPREG_PRL_MASK		(0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
             : #define SPIBAR_BFPREG_SBRS		(1 << 31)
can't we move this bit definition right after Register definition, in that way, it looks good


PS24, Line 144: /* Programmable options for Set STRAP MSG LOCK (0xF0) Register */
              : #define SPIBAR_RESET_LOCK_DISABLE	0 /* Set_Strap Lock(SSL) Bit=0 */
              : #define SPIBAR_RESET_LOCK_ENABLE	1 /* Set_Strap Lock(SSL) Bit=1 */
              : 
              : /* Programmable options for Set STRAP MSG Control (0xF4) Register*/
              : #define SPIBAR_RESET_CTRL_SSMC		1 /* Set_Strap Mux Select(SSMS) Bit=1*/
i guess these are SPI additional registers, then call out like this 
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */


https://review.coreboot.org/#/c/18557/24/src/soc/intel/common/block/include/intelblocks/fast_spi.h
File src/soc/intel/common/block/include/intelblocks/fast_spi.h:

PS24, Line 66:  * Program temporary BAR for FAST_SPI in case any of the stages before ramstage need
             :  * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
             :  * enumeration. Also, Disable the BIOS write protect and Enable Prefetching and Caching.
             :  */
>80


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Gerrit-MessageType: comment
Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Gerrit-PatchSet: 24
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati at intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.corp-partner.google.com>
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