[coreboot-gerrit] Change in coreboot[master]: nb/pineview/raminit: Fix raminit failing on hot reset path

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19337 )

Change subject: nb/pineview/raminit: Fix raminit failing on hot reset path
......................................................................

nb/pineview/raminit: Fix raminit failing on hot reset path

On hot reset some thing ought not to run:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp

TESTED on Intel d510mo.

Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/intel/d510mo/romstage.c
M src/northbridge/intel/pineview/raminit.c
2 files changed, 42 insertions(+), 30 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/19337/1

diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 3209d81..d39d2f6 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -121,7 +121,10 @@
 	post_code(0x30);
 
 	printk(BIOS_DEBUG, "Initializing memory\n");
-	sdram_initialize(0, spd_addrmap);
+	if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
+		sdram_initialize(BOOT_PATH_RESET, spd_addrmap);
+	else
+		sdram_initialize(BOOT_PATH_NORMAL, spd_addrmap);
 	printk(BIOS_DEBUG, "Memory initialized\n");
 
 	post_code(0x31);
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index a45b4da..7e24723 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -569,29 +569,30 @@
 	PRINTK_DEBUG("Drive Memory at %dMHz with CAS = %d clocks\n", ddr_reg_to_mhz(s->selected_timings.mem_clock), s->selected_timings.CAS);
 
 	// Set memory frequency
-	MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x1;
-	reg32 = (MCHBAR32(0xc00) & (~0x70)) | (1 << 10);
-	if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
-		reg8 = 3;
-	} else {
-		reg8 = 2;
-	}
-	reg32 |= reg8 << 4;
-	MCHBAR32(0xc00) = reg32;
-	s->selected_timings.mem_clock = ((MCHBAR32(0xc00) >> 4) & 0x7) - 2;
-	if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
-		PRINTK_DEBUG("MCH validated at 800MHz\n");
-		s->nodll = 0;
-		s->maxpi = 63;
-		s->pioffset = 0;
-	} else if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
-		PRINTK_DEBUG("MCH validated at 667MHz\n");
-		s->nodll = 1;
-		s->maxpi = 15;
-		s->pioffset = 1;
-	} else {
-		PRINTK_DEBUG("MCH set to unknown (%02x)\n",
-			(uint8_t) s->selected_timings.mem_clock & 0xff);
+	if (s->boot_path != BOOT_PATH_RESET) {
+		MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x1;
+		reg32 = (MCHBAR32(0xc00) & (~0x70)) | (1 << 10);
+		if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz)
+			reg8 = 3;
+		else
+			reg8 = 2;
+		reg32 |= reg8 << 4;
+		MCHBAR32(0xc00) = reg32;
+		s->selected_timings.mem_clock =	((MCHBAR32(0xc00) >> 4) & 0x7) - 2;
+		if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
+			PRINTK_DEBUG("MCH validated at 800MHz\n");
+			s->nodll = 0;
+			s->maxpi = 63;
+			s->pioffset = 0;
+		} else if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+			PRINTK_DEBUG("MCH validated at 667MHz\n");
+			s->nodll = 1;
+			s->maxpi = 15;
+			s->pioffset = 1;
+		} else {
+			PRINTK_DEBUG("MCH set to unknown (%02x)\n",
+				(uint8_t) s->selected_timings.mem_clock & 0xff);
+		}
 	}
 }
 
@@ -676,7 +677,8 @@
 		reg8 = 1;
 		reg16 = (1 << 8) | (1 << 5);
 	}
-	MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16;
+	if (s->boot_path != BOOT_PATH_RESET)
+		MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16;
 
 	MCHBAR32(0x220) = 0x58001117;
 	MCHBAR32(0x248) = (MCHBAR32(0x248) | (1 << 23));
@@ -2578,18 +2580,25 @@
 	sdram_timings(&si);
 	PRINTK_DEBUG("Done timings (dqs dll enabled)\n");
 
-	sdram_dlltiming(&si);
-	PRINTK_DEBUG("Done dlltiming\n");
+	if (si.boot_path != BOOT_PATH_RESET) {
+		sdram_dlltiming(&si);
+		PRINTK_DEBUG("Done dlltiming\n");
+	}
 
 	hpet_udelay(200000);
 
-	sdram_rcomp(&si);
-	PRINTK_DEBUG("Done RCOMP\n");
+	if (si.boot_path != BOOT_PATH_RESET) {
+		sdram_rcomp(&si);
+		PRINTK_DEBUG("Done RCOMP\n");
+	}
 
 	sdram_odt(&si);
 	PRINTK_DEBUG("Done odt\n");
 
-	while ((MCHBAR8(0x130) & 0x1) != 0);
+	if (si.boot_path != BOOT_PATH_RESET) {
+		while ((MCHBAR8(0x130) & 0x1) != 0)
+			;
+	}
 
 	sdram_mmap(&si);
 	PRINTK_DEBUG("Done mmap\n");

-- 
To view, visit https://review.coreboot.org/19337
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>