[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19280 )

Change subject: sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used
......................................................................


sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used

Do not map LPC ROM into the system memory space when SPI Flash
is configured instead of an LPC ROM.

This resolves a long-standing hard boot hang issue on the ASUS
KGPE-D16 and related systems; in a nutshell, the incorrectly
mapped LPC ROM overrode low memory required by ramstage, causing
decompressed ramstage layout-dependent vectoring to romstage code
and subsequent execution of random sections of romstage.  Sometimes
these random sections of romstage reconfigured the hardware in such
a way that it could not access SPI Flash on the next boot attempt.

Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574
Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
Reviewed-on: https://review.coreboot.org/19280
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot at felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Daniel Kulesz <daniel.ina1 at googlemail.com>
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 6 insertions(+), 8 deletions(-)

Approvals:
  Felix Held: Looks good to me, approved
  Raptor Engineering Automated Test Stand: Verified
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Daniel Kulesz: Looks good to me, but someone else must approve



diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index dfa4102..e77db5c 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -44,15 +44,13 @@
 
 	dev = PCI_DEV(0, 0x14, 3);
 
-	/* The LPC settings below work for SPI flash as well;
-	 * the hardware does not distinguish between LPC and SPI flash ROM
-	 * aside from offering additional side-channel access to SPI flash
-	 * via a separate register-based interface.
-	 */
-
-	/* Decode variable LPC ROM address ranges 1 and 2. */
 	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
-	reg8 |= (1 << 3) | (1 << 4);
+	if (IS_ENABLED(CONFIG_SPI_FLASH))
+		/* Disable decode of variable LPC ROM address ranges 1 and 2. */
+		reg8 &= ~((1 << 3) | (1 << 4));
+	else
+		/* Decode variable LPC ROM address ranges 1 and 2. */
+		reg8 |= (1 << 3) | (1 << 4);
 	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
 
 	/* LPC ROM address range 1: */

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Timothy Pearson <tpearson at raptorengineering.com>
Gerrit-Reviewer: Daniel Kulesz <daniel.ina1 at googlemail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot at felixheld.de>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
Gerrit-Reviewer: build bot (Jenkins)