[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/gma: Setup OpRegion in nb code

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19310 )

Change subject: nb/intel/sandybridge/gma: Setup OpRegion in nb code
......................................................................

nb/intel/sandybridge/gma: Setup OpRegion in nb code

Setup IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already hab been setup by SSDT injection.

Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/gma.c
M src/southbridge/intel/bd82x6x/lpc.c
2 files changed, 28 insertions(+), 6 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/19310/1

diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index dcc992c..6f319f3 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -649,6 +649,33 @@
 	drivers_intel_gma_displays_ssdt_generate(gfx);
 }
 
+static unsigned long
+gma_write_acpi_tables(struct device *const dev,
+					  unsigned long current,
+					  struct acpi_rsdp *const rsdp)
+{
+	igd_opregion_t *opregion;
+	global_nvs_t *gnvs;
+
+	opregion = igd_make_opregion();
+	if (opregion) {
+		/* GNVS has been already setup */
+		gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+		if (gnvs) {
+			/* IGD OpRegion Base Address */
+			gnvs->aslb = (u32)opregion;
+		} else {
+			printk(BIOS_ERR, "Error: GNVS table not found.\n");
+		}
+	}
+
+	current = acpi_align_current(current);
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+
+	return current;
+}
+
 /* called by pci set_vga_bridge function */
 static void gma_func0_disable(struct device *dev)
 {
@@ -676,6 +703,7 @@
 	.enable			= 0,
 	.disable		= gma_func0_disable,
 	.ops_pci		= &gma_pci_ops,
+	.write_acpi_tables	= gma_write_acpi_tables,
 };
 
 static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112,
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 623482e..c9fee89 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -654,10 +654,6 @@
 static void southbridge_inject_dsdt(device_t dev)
 {
 	global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
-	void *opregion;
-
-	/* Calling northbridge code as gnvs contains opregion address.  */
-	opregion = igd_make_opregion();
 
 	if (gnvs) {
 		const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -676,8 +672,6 @@
 		chromeos_init_vboot(&(gnvs->chromeos));
 #endif
 
-		/* IGD OpRegion Base Address */
-		gnvs->aslb = (u32)opregion;
 		/* And tell SMI about it */
 		smm_setup_structures(gnvs, NULL, NULL);
 

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>