[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used

[Timothy Pearson (Code Review)]

Timothy Pearson has uploaded a new change for review. ( https://review.coreboot.org/19280 )

Change subject: sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used
......................................................................

sb/amd/sb700: Disable LPC ROM mapping when SPI Flash is used

Do not map LPC ROM into the system memory space when SPI Flash
is configured instead of an LPC ROM.

This resolves a long-standing hard boot hang issue on the ASUS
KGPE-D16 and related systems; in a nutshell, the incorrectly
mapped LPC ROM override low memory required by ramstage, causing
decompressed ramstage layout-dependent vectoring to romstage code
and subsequent execution of random sections of romstage.

Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574
Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 12 insertions(+), 10 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/19280/1

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index dfa4102..0564911 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -44,16 +44,18 @@
 
 	dev = PCI_DEV(0, 0x14, 3);
 
-	/* The LPC settings below work for SPI flash as well;
-	 * the hardware does not distinguish between LPC and SPI flash ROM
-	 * aside from offering additional side-channel access to SPI flash
-	 * via a separate register-based interface.
-	 */
-
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+	if (IS_ENABLED(CONFIG_SPI_FLASH)) {
+		/* Disable decode of variable LPC ROM address ranges 1 and 2. */
+		reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
+		reg8 &= ~((1 << 3) | (1 << 4));
+		pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+	}
+	else {
+		/* Decode variable LPC ROM address ranges 1 and 2. */
+		reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
+		reg8 |= (1 << 3) | (1 << 4);
+		pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+	}
 
 	/* LPC ROM address range 1: */
 	/* Enable LPC ROM range mirroring start at 0x000e(0000). */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I115e5d834f0ca99c2d9dbb5b9b5badbea1d98574
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Timothy Pearson <tpearson at raptorengineering.com>