[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_A...

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19277 )

Change subject: soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESS
......................................................................


soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESS

With recent change to use common block PCR (ccd8700c),
IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card
change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS
slipped into the tree. Fix this by replacing all occurrences of
IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS.

Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
Reviewed-on: https://review.coreboot.org/19277
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Reviewed-by: Martin Roth <martinroth at google.com>
---
M src/soc/intel/apollolake/acpi/gpiolib.asl
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Venkateswarlu V Vinjamuri: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved



diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl
index 0acfb67..a4d4b00 100644
--- a/src/soc/intel/apollolake/acpi/gpiolib.asl
+++ b/src/soc/intel/apollolake/acpi/gpiolib.asl
@@ -71,7 +71,7 @@
 		/* Arg0 - GPIO portid */
 		/* Arg1 - GPIO pad offset relative to the community */
 		Store (0, Local1)
-		Or( Or (ShiftLeft (Arg0, 16), CONFIG_IOSF_BASE_ADDRESS),
+		Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS),
 					Local1, Local1)
 		Or( Add (PAD_CFG_BASE, Multiply (Arg1, 8)), Local1, Local1)
 		Return (Local1)
@@ -93,7 +93,7 @@
 		Store (CHSA (Arg1), Local1)
 
 		OperationRegion (SHO0, SystemMemory, Or ( Or
-			(CONFIG_IOSF_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4)
+			(CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4)
 		Field (SHO0, AnyAcc, NoLock, Preserve) {
 			TEMP, 32
 		}
@@ -109,7 +109,7 @@
 		Store (CHSA (Arg1), Local1)
 
 		OperationRegion (SHO0, SystemMemory, Or ( Or
-			(CONFIG_IOSF_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4)
+			(CONFIG_PCR_BASE_ADDRESS, ShiftLeft (Arg0, 16)), Local1), 4)
 		Field (SHO0, AnyAcc, NoLock, Preserve) {
 			TEMP, 32
 		}

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Stefan Reinauer <reinauer at chromium.org>
Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Gerrit-Reviewer: build bot (Jenkins)