[coreboot-gerrit] Change in coreboot[master]: mainboard/google/eve: Set UART0 to skip initialization in FSP

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded a new change for review. ( https://review.coreboot.org/19264 )

Change subject: mainboard/google/eve: Set UART0 to skip initialization in FSP
......................................................................

mainboard/google/eve: Set UART0 to skip initialization in FSP

Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.

Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.

BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.

Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/eve/gpio.h
M src/mainboard/google/eve/mainboard.c
3 files changed, 1 insertion(+), 12 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/19264/1

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 7db97b7..99ddb2e 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -204,7 +204,7 @@
 		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 		[PchSerialIoIndexSpi0]  = PchSerialIoPci,
 		[PchSerialIoIndexSpi1]  = PchSerialIoPci,
-		[PchSerialIoIndexUart0] = PchSerialIoPci,
+		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index c4c73ae..6da8244 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -231,13 +231,6 @@
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 };
 
-static const struct pad_config late_gpio_table[] = {
-/* UART0_RXD */		PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */		PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
-/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
-/* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
-};
-
 #endif
 
 #endif
diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c
index dda0cfa..d30eff2 100644
--- a/src/mainboard/google/eve/mainboard.c
+++ b/src/mainboard/google/eve/mainboard.c
@@ -19,10 +19,7 @@
 #include <device/device.h>
 #include <ec/ec.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <gpio.h>
-#include <soc/gpio.h>
 #include <soc/nhlt.h>
-#include "gpio.h"
 
 static const char *oem_id_maxim = "GOOGLE";
 static const char *oem_table_id_maxim = "EVEMAX";
@@ -30,7 +27,6 @@
 static void mainboard_init(device_t dev)
 {
 	mainboard_ec_init();
-	gpio_configure_pads(late_gpio_table, ARRAY_SIZE(late_gpio_table));
 }
 
 static unsigned long mainboard_write_acpi_tables(

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>