[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801lx: Generate default fadt and madt
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed Apr 12 15:11:13 CEST 2017
Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19253 )
Change subject: sb/intel/i82801lx: Generate default fadt and madt
......................................................................
sb/intel/i82801lx: Generate default fadt and madt
Copied from i82801gx.
Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/i82801lx/Kconfig
M src/southbridge/intel/i82801lx/chip.h
M src/southbridge/intel/i82801lx/lpc.c
3 files changed, 151 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19253/1
diff --git a/src/southbridge/intel/i82801lx/Kconfig b/src/southbridge/intel/i82801lx/Kconfig
index 39d08c7..3fcd7b0 100644
--- a/src/southbridge/intel/i82801lx/Kconfig
+++ b/src/southbridge/intel/i82801lx/Kconfig
@@ -25,6 +25,7 @@
select HAVE_USBDEBUG_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select HAVE_INTEL_FIRMWARE
+ select COMMON_FADT
if SOUTHBRIDGE_INTEL_I82801LX
diff --git a/src/southbridge/intel/i82801lx/chip.h b/src/southbridge/intel/i82801lx/chip.h
index 0409da6..b98107d 100644
--- a/src/southbridge/intel/i82801lx/chip.h
+++ b/src/southbridge/intel/i82801lx/chip.h
@@ -73,6 +73,9 @@
int c4onc3_enable:1;
int c5_enable : 1;
int c6_enable : 1;
+ int c3_latency;
+ int p_cnt_throttling_supported:1;
+ int docking_supported:1;
int throttle_duty : 3;
diff --git a/src/southbridge/intel/i82801lx/lpc.c b/src/southbridge/intel/i82801lx/lpc.c
index 38d2ee1..39ce071 100644
--- a/src/southbridge/intel/i82801lx/lpc.c
+++ b/src/southbridge/intel/i82801lx/lpc.c
@@ -28,6 +28,7 @@
#include <cpu/cpu.h>
#include <cpu/x86/smm.h>
#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
#include <cbmem.h>
#include <string.h>
#include "i82801lx.h"
@@ -469,6 +470,152 @@
#endif
}
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* LAPIC_NMI */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 0,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 1, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+
+ return current;
+}
+
+void acpi_fill_fadt(acpi_fadt_t *fadt)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ config_t *chip = dev->chip_info;
+ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x20;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x28;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 0;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 0;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 0;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x32;
+
+ fadt->model = 1;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = chip->c3_latency;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ if (chip->p_cnt_throttling_supported)
+ fadt->duty_width = 3;
+ else
+ fadt->duty_width = 0;
+ fadt->iapc_boot_arch = 0x03;
+ fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
+ | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
+ | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
+ | ACPI_FADT_C2_MP_SUPPORTED);
+ if (chip->docking_supported)
+ fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
+}
+
static void i82801lx_lpc_read_resources(device_t dev)
{
int i, io_index = 0;
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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