[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801lx: Hook up to northbridge and smmrelocate
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed Apr 12 15:11:11 CEST 2017
Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19250 )
Change subject: sb/intel/i82801lx: Hook up to northbridge and smmrelocate
......................................................................
sb/intel/i82801lx: Hook up to northbridge and smmrelocate
Removes DMI setup and setting up default BARs since this is done in
northbridge code.
Adds setting up RCBA in bootblock just like i82801gx.
Change-Id: I493866d7b114ce21d8221c9e26af61a0c7c83365
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/x86/smm/smmrelocate.S
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/southbridge/intel/i82801lx/Makefile.inc
M src/southbridge/intel/i82801lx/bootblock.c
D src/southbridge/intel/i82801lx/dmi_setup.c
D src/southbridge/intel/i82801lx/early_init.c
M src/southbridge/intel/i82801lx/i82801lx.h
9 files changed, 18 insertions(+), 206 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/19250/1
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 2fe0156..2474b63 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -29,6 +29,9 @@
#include "../../../soc/intel/sch/sch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
#include "../../../southbridge/intel/i82801ix/i82801ix.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_I82801LX
+#include "../../../southbridge/intel/i82801lx/i82801lx.h"
+
#else
#error "Southbridge needs SMM handler support."
#endif
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index a556adc..1c0a997 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -17,7 +17,11 @@
#include <stdint.h>
#include <arch/io.h>
#include "iomap.h"
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801LX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
+#else
+#include <southbridge/intel/i82801lx/i82801lx.h> /* DEFAULT_PMBASE */
+#endif
#include <pc80/mc146818rtc.h>
#include "x4x.h"
#include <cbmem.h>
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 7d352f1..469df1e 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -23,7 +23,11 @@
#include <halt.h>
#include <lib.h>
#include "iomap.h"
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
+#else
+#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
+#endif
#include "x4x.h"
#include <pc80/mc146818rtc.h>
#include <spd.h>
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index eca7189..c35d477 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -21,9 +21,10 @@
#include <commonlib/helpers.h>
#include <delay.h>
#include <pc80/mc146818rtc.h>
-/* This northbridge can also occur with ICH10 */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h>
+#else
+#include <southbridge/intel/i82801lx/i82801lx.h>
#endif
#include "iomap.h"
#include "x4x.h"
diff --git a/src/southbridge/intel/i82801lx/Makefile.inc b/src/southbridge/intel/i82801lx/Makefile.inc
index 0d622c8..365e8cc 100644
--- a/src/southbridge/intel/i82801lx/Makefile.inc
+++ b/src/southbridge/intel/i82801lx/Makefile.inc
@@ -36,8 +36,6 @@
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += early_init.c
romstage-y += early_smbus.c
-romstage-y += dmi_setup.c
endif
diff --git a/src/southbridge/intel/i82801lx/bootblock.c b/src/southbridge/intel/i82801lx/bootblock.c
index 6252712..7afb2f0 100644
--- a/src/southbridge/intel/i82801lx/bootblock.c
+++ b/src/southbridge/intel/i82801lx/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include "i82801lx.h"
static void enable_spi_prefetch(void)
{
@@ -31,4 +32,8 @@
static void bootblock_southbridge_init(void)
{
enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
+ (uintptr_t)DEFAULT_RCBA | 1);
}
diff --git a/src/southbridge/intel/i82801lx/dmi_setup.c b/src/southbridge/intel/i82801lx/dmi_setup.c
deleted file mode 100644
index d889a1c..0000000
--- a/src/southbridge/intel/i82801lx/dmi_setup.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 secunet Security Networks AG
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <console/console.h>
-#include <northbridge/intel/gm45/gm45.h>
-#include "i82801lx.h"
-
-/* VC1 Port Arbitration Table */
-static const u8 vc1_pat[] = {
- 0x0f, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x0f, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0xf0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x0f,
- 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xf0, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0x0f, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x0f, 0x00,
- 0x00, 0x00, 0x00, 0x00,
- 0xf0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x0f,
- 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xf0, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00,
-};
-void i82801lx_dmi_setup(void)
-{
- int i;
- u32 reg32;
-
- RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16);
-
- RCBA32(0x0088) = 0x00109000;
- RCBA16(0x01fc) = 0x060b;
- RCBA32(0x01f4) = 0x86000040;
- RCBA8 (0x0220) = 0x45;
- RCBA32(0x2024) &= ~(1 << 7);
-
-
- /* VC1 setup for isochronous transfers: */
-
- /* Set VC1 virtual channel id to 1. */
- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24);
- /* Enable TC7 traffic on VC1. */
- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7);
- /* Disable TC7-TC1 traffic on VC0. */
- RCBA32(RCBA_V0CTL) &= ~(0x7f << 1);
- /* TC7-TC1 traffic on PCIe root ports will be disabled in pci driver. */
-
- /* Set table type to time-based WRR. */
- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17);
- /* Program port arbitration table. */
- for (i = 0; i < sizeof(vc1_pat); ++i)
- RCBA8(RCBA_PAT + i) = vc1_pat[i];
- /* Load port arbitration table. */
- RCBA32(RCBA_V1CTL) |= (1 << 16);
-
- /* Enable VC1. */
- RCBA32(RCBA_V1CTL) |= (1 << 31);
-
-
- /* Setup RCRB: */
-
- /* Set component id to 2 for southbridge, northbridge has id 1. */
- RCBA8(RCBA_ESD + 2) = 2;
- /* Set target port number and target component id of the northbridge. */
- RCBA8(RCBA_ULD + 3) = 1;
- RCBA8(RCBA_ULD + 2) = 1;
- /* Set target rcrb base address, i.e. DMIBAR. */
- RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;
-
- /* Enable ASPM. */
- if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {
- reg32 = RCBA32(RCBA_DMC);
- /* Enable mobile specific power saving (set this first). */
- reg32 = (reg32 & ~(3 << 10)) | (1 << 10);
- RCBA32(RCBA_DMC) = reg32;
- /* Enable DMI power savings. */
- reg32 |= (1 << 19);
- RCBA32(RCBA_DMC) = reg32;
- /* Advertise L0s and L1. */
- RCBA32(RCBA_LCAP) |= (3 << 10);
- /* Enable L0s and L1. */
- RCBA32(RCBA_LCTL) |= (3 << 0);
- } else {
- /* Enable DMI power savings. */
- RCBA32(RCBA_DMC) |= (1 << 19);
- /* Advertise L0s only. */
- RCBA32(RCBA_LCAP) = (RCBA32(RCBA_LCAP) & ~(3<<10)) | (1<<10);
- /* Enable L0s only. */
- RCBA32(RCBA_LCTL) = (RCBA32(RCBA_LCTL) & ~(3<< 0)) | (1<< 0);
- }
-}
-
-/* Should be called after VC1 has been enabled on both sides. */
-void i82801lx_dmi_poll_vc1(void)
-{
- int timeout;
-
- timeout = 0x7ffff;
- printk(BIOS_DEBUG, "ICH9 waits for VC1 negotiation... ");
- while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {}
- if (!timeout)
- printk(BIOS_DEBUG, "timeout!\n");
- else
- printk(BIOS_DEBUG, "done.\n");
-
- /* Check for x2 DMI link. */
- if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) {
- printk(BIOS_DEBUG, "x2 DMI link detected.\n");
- RCBA32(0x2024) = (RCBA32(0x2024) & ~(7 << 21)) | (3 << 21);
- RCBA16(0x20c4) |= (1 << 15);
- RCBA16(0x20e4) |= (1 << 15);
- /* TODO: Maybe we have to save and
- restore these settings across S3. */
- }
-
- timeout = 0x7ffff;
- printk(BIOS_DEBUG, "ICH9 waits for port arbitration table update... ");
- while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {}
- if (!timeout)
- printk(BIOS_DEBUG, "timeout!\n");
- else
- printk(BIOS_DEBUG, "done.\n");
-}
diff --git a/src/southbridge/intel/i82801lx/early_init.c b/src/southbridge/intel/i82801lx/early_init.c
deleted file mode 100644
index a02854f..0000000
--- a/src/southbridge/intel/i82801lx/early_init.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 secunet Security Networks AG
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include "i82801lx.h"
-
-void i82801lx_early_init(void)
-{
- const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
-
- /* Set up RCBA. */
- pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-
- /* Set up PMBASE. */
- pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
- /* Enable PMBASE. */
- pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);
-
- /* Set up GPIOBASE. */
- pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
- /* Enable GPIO. */
- pci_write_config8(d31f0, D31F0_GPIO_CNTL,
- pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10);
-
- /* Reset watchdog. */
- outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */
- outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */
-
- /* Enable upper 128bytes of CMOS. */
- RCBA32(0x3400) = (1 << 2);
-
- /* Initialize power management initialization
- register early as it affects reboot behavior. */
- /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
- and 0xe (required if ME is disabled but present), bit 31 locks it.
- The other bits are 'must write'. */
- u8 reg8 = pci_read_config8(d31f0, 0xac);
- reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
- pci_write_config8(d31f0, 0xac, reg8);
-
- /* TODO: If RTC power failed, reset RTC state machine
- (set, then reset RTC 0x0b bit7) */
-
- /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
- before they get cleared. */
-}
diff --git a/src/southbridge/intel/i82801lx/i82801lx.h b/src/southbridge/intel/i82801lx/i82801lx.h
index 2167e77..be8a5b2 100644
--- a/src/southbridge/intel/i82801lx/i82801lx.h
+++ b/src/southbridge/intel/i82801lx/i82801lx.h
@@ -230,9 +230,6 @@
#if defined(__PRE_RAM__)
void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
-void i82801lx_early_init(void);
-void i82801lx_dmi_setup(void);
-void i82801lx_dmi_poll_vc1(void);
int southbridge_detect_s3_resume(void);
#endif
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I493866d7b114ce21d8221c9e26af61a0c7c83365
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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