[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801lx: Add Interrupt pin and routing RCBA offset...

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19255 )

Change subject: sb/intel/i82801lx: Add Interrupt pin and routing RCBA offsets macros
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sb/intel/i82801lx: Add Interrupt pin and routing RCBA offsets macros

Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/i82801lx/i82801lx.h
1 file changed, 17 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19255/1

diff --git a/src/southbridge/intel/i82801lx/i82801lx.h b/src/southbridge/intel/i82801lx/i82801lx.h
index be8a5b2..6c99351 100644
--- a/src/southbridge/intel/i82801lx/i82801lx.h
+++ b/src/southbridge/intel/i82801lx/i82801lx.h
@@ -195,6 +195,23 @@
 #define RCBA_FDSW		0x3420
 #define RCBA_MAP		0x35f0 /* UHCI controller #6 remapping */
 
+#define D31IP		0x3100	/* 32bit */
+#define D30IP		0x3104	/* 32bit R0: does not generate interrupt */
+#define D29IP		0x3108	/* 32bit */
+#define D28IP		0x310c	/* 32bit */
+#define D27IP		0x3110	/* 32bit */
+#define D26IP		0x3114  /* 32bit */
+#define D25IP		0x3114  /* 32bit */
+
+#define D31IR		0x3140	/* 16bit */
+#define D30IR		0x3142	/* 16bit R0: does not generate interrupt */
+#define D29IR		0x3144	/* 16bit */
+#define D28IR		0x3146	/* 16bit */
+#define D27IR		0x3148	/* 16bit */
+#define D26IR		0x314c	/* 16bit */
+#define D25IR		0x3150	/* 16bit */
+#define OIC		0x31ff	/*  8bit */
+
 #define BUC_LAND	(1 <<  5) /* LAN */
 #define FD_SAD2		(1 << 25) /* SATA #2 */
 #define FD_TTD		(1 << 24) /* Thermal Throttle */

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>