[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801lx: Add function to detect s3 resume

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19252 )

Change subject: sb/intel/i82801lx: Add function to detect s3 resume
......................................................................

sb/intel/i82801lx: Add function to detect s3 resume

File copied from i82801gx.

Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/i82801lx/Makefile.inc
A src/southbridge/intel/i82801lx/early_lpc.c
2 files changed, 55 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/19252/1

diff --git a/src/southbridge/intel/i82801lx/Makefile.inc b/src/southbridge/intel/i82801lx/Makefile.inc
index 365e8cc..653b477 100644
--- a/src/southbridge/intel/i82801lx/Makefile.inc
+++ b/src/southbridge/intel/i82801lx/Makefile.inc
@@ -37,5 +37,6 @@
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c
+romstage-y += early_lpc.c
 
 endif
diff --git a/src/southbridge/intel/i82801lx/early_lpc.c b/src/southbridge/intel/i82801lx/early_lpc.c
new file mode 100644
index 0000000..e85ecf0
--- /dev/null
+++ b/src/southbridge/intel/i82801lx/early_lpc.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <timestamp.h>
+#include <cpu/x86/tsc.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include "i82801lx.h"
+
+uint64_t get_initial_timestamp(void)
+{
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+	return tsc_to_uint64(base_time);
+}
+
+int southbridge_detect_s3_resume(void)
+{
+	u32 reg32;
+
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+		if (!acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+			return 1;
+		}
+	}
+
+	return 0;
+}

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>