[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use LPSS common library
Martin Roth (Code Review)
gerrit at coreboot.org
Tue Apr 11 16:59:35 CEST 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19153 )
Change subject: soc/intel/skylake: Use LPSS common library
......................................................................
soc/intel/skylake: Use LPSS common library
Use lpss common library to program reset and
clock register for lpss modules.
Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
Reviewed-on: https://review.coreboot.org/19153
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik at intel.com>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/i2c.c
M src/soc/intel/skylake/bootblock/uart.c
M src/soc/intel/skylake/include/soc/serialio.h
4 files changed, 11 insertions(+), 30 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
Subrata Banik: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index e22f1e3..e597d62 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -51,6 +51,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
+ select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c
index 11d145c..59cb5c8 100644
--- a/src/soc/intel/skylake/bootblock/i2c.c
+++ b/src/soc/intel/skylake/bootblock/i2c.c
@@ -18,11 +18,11 @@
#include <device/device.h>
#include <device/i2c.h>
#include <device/pci_def.h>
+#include <intelblocks/lpss.h>
#include <soc/intel/common/lpss_i2c.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/bootblock.h>
-#include <soc/serialio.h>
#include "chip.h"
uintptr_t lpss_i2c_base_address(unsigned int bus)
@@ -49,8 +49,6 @@
pci_devfn_t dev;
int devfn;
uintptr_t base;
- uint32_t value;
- void *reg;
/* Find the PCI device for this bus controller */
devfn = i2c_bus_to_devfn(bus);
@@ -77,11 +75,7 @@
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Take device out of reset */
- reg = (void *)(base + SIO_REG_PPR_RESETS);
- value = read32(reg);
- value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
- SIO_REG_PPR_RESETS_IDMA;
- write32(reg, value);
+ lpss_reset_release(base);
/* Initialize the controller */
lpss_i2c_init(bus, &config->i2c[bus]);
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index d51d179..cf06359 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -18,12 +18,12 @@
#include <arch/io.h>
#include <console/uart.h>
#include <device/pci_def.h>
+#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <stdint.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
-#include <soc/serialio.h>
#include <gpio.h>
/* Serial IO UART controller legacy mode */
@@ -31,6 +31,10 @@
#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0)
#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
+
+/* Clock divider parameters for 115200 baud rate */
+#define CLOCK_DIV_M_VAL 0x30
+#define CLOCK_DIV_N_VAL 0xc35
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
@@ -42,7 +46,7 @@
{
device_t dev = PCH_DEV_UART2;
u32 tmp;
- u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+ uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
/* Set configured UART2 base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
@@ -53,21 +57,14 @@
pci_write_config32(dev, PCI_COMMAND, tmp);
/* Take UART2 out of reset */
- tmp = read32(base + SIO_REG_PPR_RESETS);
- tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
- SIO_REG_PPR_RESETS_IDMA;
- write32(base + SIO_REG_PPR_RESETS, tmp);
+ lpss_reset_release(base);
/*
* Set M and N divisor inputs and enable clock.
* Main reference frequency to UART is:
* 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
*/
- tmp = read32(base + SIO_REG_PPR_CLOCK);
- tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
- (SIO_REG_PPR_CLOCK_N_DIV << 16) |
- (SIO_REG_PPR_CLOCK_M_DIV << 1);
- write32(base + SIO_REG_PPR_CLOCK, tmp);
+ lpss_clk_update(base, CLOCK_DIV_M_VAL, CLOCK_DIV_N_VAL);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
diff --git a/src/soc/intel/skylake/include/soc/serialio.h b/src/soc/intel/skylake/include/soc/serialio.h
index d66bf80..a07f29c 100644
--- a/src/soc/intel/skylake/include/soc/serialio.h
+++ b/src/soc/intel/skylake/include/soc/serialio.h
@@ -17,17 +17,6 @@
#ifndef _SERIALIO_H_
#define _SERIALIO_H_
-#define SIO_REG_PPR_CLOCK 0x200
-#define SIO_REG_PPR_CLOCK_EN (1 << 0)
-#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31)
-#define SIO_REG_PPR_CLOCK_N_DIV 0xc35
-#define SIO_REG_PPR_CLOCK_M_DIV 0x30
-
-#define SIO_REG_PPR_RESETS 0x204
-#define SIO_REG_PPR_RESETS_FUNC (1 << 0)
-#define SIO_REG_PPR_RESETS_APB (1 << 1)
-#define SIO_REG_PPR_RESETS_IDMA (1 << 2)
-
typedef enum {
PchSerialIoDisabled,
PchSerialIoAcpi,
--
To view, visit https://review.coreboot.org/19153
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: merged
Gerrit-Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
More information about the coreboot-gerrit
mailing list