[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Split AC/DC settings for Deep Sx config
Duncan Laurie (Code Review)
gerrit at coreboot.org
Tue Apr 11 07:13:37 CEST 2017
Duncan Laurie has uploaded a new change for review. ( https://review.coreboot.org/19239 )
Change subject: soc/intel/skylake: Split AC/DC settings for Deep Sx config
......................................................................
soc/intel/skylake: Split AC/DC settings for Deep Sx config
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states. However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.
To address this split the setting and add a separate config for Deep Sx in
AC and DC states.
All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.
BUG=b:36723679
BRANCH=none
TEST=This commit has no functional changes and compiles for all boards.
Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/chell/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/poppy/devicetree.cb
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/pmc.c
8 files changed, 37 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/19239/1
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 477a8aa..5df9ea6 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -1,8 +1,10 @@
chip soc/intel/skylake
# Enable deep Sx states
- register "deep_s3_enable" = "0"
- register "deep_s5_enable" = "1"
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# GPE configuration
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 427ba6b..f995ab7 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -1,8 +1,10 @@
chip soc/intel/skylake
# Enable deep Sx states
- register "deep_s3_enable" = "1"
- register "deep_s5_enable" = "1"
+ register "deep_s3_enable_ac" = "1"
+ register "deep_s3_enable_dc" = "1"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
# GPE configuration
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index e498dc9..ee02177 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -1,8 +1,10 @@
chip soc/intel/skylake
# Deep Sx states
- register "deep_s3_enable" = "0"
- register "deep_s5_enable" = "1"
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
# GPE configuration
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index f7a2e52..d4155ea 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -1,8 +1,10 @@
chip soc/intel/skylake
# Enable deep Sx states
- register "deep_s3_enable" = "0"
- register "deep_s5_enable" = "1"
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# GPE configuration
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index fcf1066..9ff919d 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -1,8 +1,10 @@
chip soc/intel/skylake
# Deep Sx states
- register "deep_s3_enable" = "0"
- register "deep_s5_enable" = "1"
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
# GPE configuration
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index b3b999f..a75f526 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -610,7 +610,8 @@
* Chipset state in the suspend well (but not RTC) is lost in Deep S3
* so enable Deep S3 wake events that are configured by the mainboard
*/
- if (ps->prev_sleep_state == ACPI_S3 && config->deep_s3_enable) {
+ if (ps->prev_sleep_state == ACPI_S3 &&
+ (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) {
pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
gpe0_std |= LAN_WAK_EN;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index ce5fe22..cd461d4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -86,9 +86,11 @@
/* Enable DPTF support */
int dptf_enable;
- /* Deep SX enable for both AC and DC */
- int deep_s3_enable;
- int deep_s5_enable;
+ /* Deep SX enables */
+ int deep_s3_enable_ac;
+ int deep_s3_enable_dc;
+ int deep_s5_enable_ac;
+ int deep_s5_enable_dc;
/*
* Deep Sx Configuration
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 64df186..f3a2681 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -189,16 +189,19 @@
write32(pmcbase + offset, reg);
}
-static void config_deep_s5(int on)
+static void config_deep_s5(int on_ac, int on_dc)
{
/* Treat S4 the same as S5. */
- config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS | S4AC_GATE_SUS, 4, on);
- config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS | S5AC_GATE_SUS, 5, on);
+ config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
+ config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
+ config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
+ config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
}
-static void config_deep_s3(int on)
+static void config_deep_s3(int on_ac, int on_dc)
{
- config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS | S3AC_GATE_SUS, 3, on);
+ config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
+ config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
}
static void config_deep_sx(uint32_t deepsx_config)
@@ -226,8 +229,8 @@
reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
pch_set_acpi_mode();
- config_deep_s3(config->deep_s3_enable);
- config_deep_s5(config->deep_s5_enable);
+ config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
+ config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
config_deep_sx(config->deep_sx_config);
/* Clear registers that contain write-1-to-clear bits. */
--
To view, visit https://review.coreboot.org/19239
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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