[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add LPSS function library

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19001 )

Change subject: soc/intel/common/block: Add LPSS function library
......................................................................


soc/intel/common/block: Add LPSS function library

LPSS function library implements common register
programming under lpss.

Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
Reviewed-on: https://review.coreboot.org/19001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
A src/soc/intel/common/block/include/intelblocks/lpss.h
A src/soc/intel/common/block/lpss/Kconfig
A src/soc/intel/common/block/lpss/Makefile.inc
A src/soc/intel/common/block/lpss/lpss.c
4 files changed, 97 insertions(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
new file mode 100644
index 0000000..03a4714
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H
+#define SOC_INTEL_COMMON_BLOCK_LPSS_H
+
+#include <stdint.h>
+
+/* Gets controller out of reset */
+void lpss_reset_release(uintptr_t base);
+
+/*
+ * Update clock divider parameters. Clock frequency is
+ * configured as SOC_INTEL_COMMON_LPSS_CLOCK_MHZ * (M / N)
+ */
+void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_LPSS_H */
diff --git a/src/soc/intel/common/block/lpss/Kconfig b/src/soc/intel/common/block/lpss/Kconfig
new file mode 100644
index 0000000..f8ce731
--- /dev/null
+++ b/src/soc/intel/common/block/lpss/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_LPSS
+	bool
+	help
+	  Intel Processor common LPSS support
diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc
new file mode 100644
index 0000000..6c56c68
--- /dev/null
+++ b/src/soc/intel/common/block/lpss/Makefile.inc
@@ -0,0 +1,3 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
\ No newline at end of file
diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c
new file mode 100644
index 0000000..146fdab
--- /dev/null
+++ b/src/soc/intel/common/block/lpss/lpss.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <intelblocks/lpss.h>
+
+/* Clock register */
+#define LPSS_CLOCK_CTL_REG	0x200
+#define LPSS_CNT_CLOCK_EN	1
+#define LPSS_CNT_CLK_UPDATE	(1 << 31)
+#define LPSS_CLOCK_DIV_N(n)	(((n) & 0x7fff) << 16)
+#define LPSS_CLOCK_DIV_M(m)	(((m) & 0x7fff) << 1)
+
+/* reset register  */
+#define LPSS_RESET_CTL_REG	0x204
+
+/*
+ * Bit 1:0 controls LPSS controller reset.
+ *
+ * 00 ->LPSS Host Controller is in reset (Reset Asserted)
+ * 01/10 ->Reserved
+ * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
+ */
+
+#define LPSS_CNT_RST_RELEASE	3
+
+/* DMA Software Reset Control */
+#define LPSS_DMA_RST_RELEASE	(1 << 2)
+
+void lpss_reset_release(uintptr_t base)
+{
+	uint8_t *addr = (void *)base;
+
+	/* Take controller out of reset */
+	write32(addr + LPSS_RESET_CTL_REG, LPSS_CNT_RST_RELEASE);
+}
+
+void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
+{
+	uint8_t *addr = (void *)base;
+	uint32_t clk_sel;
+
+	addr += LPSS_CLOCK_CTL_REG;
+	clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val);
+
+	write32(addr, clk_sel | LPSS_CNT_CLK_UPDATE);
+	write32(addr, clk_sel | LPSS_CNT_CLOCK_EN);
+}

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)