[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common RTC code support

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18558 )

Change subject: soc/intel/common/block: Add Intel common RTC code support
......................................................................


soc/intel/common/block: Add Intel common RTC code support

Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.

Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
Reviewed-on: https://review.coreboot.org/18558
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Tested-by: build bot (Jenkins)
---
A src/soc/intel/common/block/include/intelblocks/rtc.h
A src/soc/intel/common/block/rtc/Kconfig
A src/soc/intel/common/block/rtc/Makefile.inc
A src/soc/intel/common/block/rtc/rtc.c
4 files changed, 57 insertions(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  Philippe Mathieu-Daudé: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified



diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h
new file mode 100644
index 0000000..1556026
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/rtc.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_RTC_H
+#define SOC_INTEL_COMMON_BLOCK_RTC_H
+
+void enable_rtc_upper_bank(void);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_RTC_H */
diff --git a/src/soc/intel/common/block/rtc/Kconfig b/src/soc/intel/common/block/rtc/Kconfig
new file mode 100644
index 0000000..d194f15
--- /dev/null
+++ b/src/soc/intel/common/block/rtc/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_RTC
+	bool
+	help
+	  Intel Processor common RTC support
diff --git a/src/soc/intel/common/block/rtc/Makefile.inc b/src/soc/intel/common/block/rtc/Makefile.inc
new file mode 100644
index 0000000..2d2d4e3
--- /dev/null
+++ b/src/soc/intel/common/block/rtc/Makefile.inc
@@ -0,0 +1 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c
diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c
new file mode 100644
index 0000000..ea99870
--- /dev/null
+++ b/src/soc/intel/common/block/rtc/rtc.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pcr_ids.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/rtc.h>
+
+/* RTC PCR configuration */
+#define PCR_RTC_CONF		0x3400
+#define PCR_RTC_CONF_UCMOS_EN	(1 << 2)
+#define PCR_RTC_CONF_LCMOS_LOCK	(1 << 3)
+#define PCR_RTC_CONF_UCMOS_LOCK	(1 << 4)
+#define PCR_RTC_CONF_RESERVED	(1 << 31)
+
+void enable_rtc_upper_bank(void)
+{
+	/* Enable upper 128 bytes of CMOS */
+	pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
+}

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Gerrit-PatchSet: 17
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude at gmail.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar at intel.com>
Gerrit-Reviewer: build bot (Jenkins)