[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use common PCR module
Martin Roth (Code Review)
gerrit at coreboot.org
Mon Apr 10 20:04:09 CEST 2017
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18674 )
Change subject: soc/intel/skylake: Use common PCR module
......................................................................
soc/intel/skylake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h
Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Reviewed-on: https://review.coreboot.org/18674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/acpi/irqlinks.asl
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/acpi/pcr.asl
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/bootblock/uart.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/include/soc/iomap.h
A src/soc/intel/skylake/include/soc/itss.h
D src/soc/intel/skylake/include/soc/pcr.h
A src/soc/intel/skylake/include/soc/pcr_ids.h
M src/soc/intel/skylake/lpc.c
D src/soc/intel/skylake/pcr.c
M src/soc/intel/skylake/pmc.c
M src/soc/intel/skylake/smihandler.c
17 files changed, 192 insertions(+), 382 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 82e5d55..ae86198 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -51,6 +51,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
+ select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_LPSS_I2C
@@ -152,6 +153,12 @@
help
Provide a monotonic timer using the 24MHz MSR counter.
+config PCR_BASE_ADDRESS
+ hex
+ default 0xfd000000
+ help
+ This option allows you to select MMIO Base Address of sideband bus.
+
config PRE_GRAPHICS_DELAY
int "Graphics initialization delay in ms"
default 0
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index cb8eb89..2ef4bba 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -22,7 +22,6 @@
bootblock-y += gspi.c
bootblock-y += monotonic_timer.c
bootblock-y += pch.c
-bootblock-y += pcr.c
bootblock-y += pmutil.c
bootblock-y += spi.c
bootblock-y += tsc_freq.c
@@ -45,7 +44,6 @@
romstage-y += monotonic_timer.c
romstage-y += me.c
romstage-y += pch.c
-romstage-y += pcr.c
romstage-y += pei_data.c
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
@@ -76,7 +74,6 @@
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
ramstage-y += pch.c
ramstage-y += pcie.c
-ramstage-y += pcr.c
ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
@@ -98,7 +95,6 @@
smm-y += cpu_info.c
smm-y += gpio.c
smm-y += monotonic_timer.c
-smm-y += pcr.c
smm-y += pch.c
smm-y += pmutil.c
smm-y += smihandler.c
diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl
index f698a1e..6a85a74 100644
--- a/src/soc/intel/skylake/acpi/irqlinks.asl
+++ b/src/soc/intel/skylake/acpi/irqlinks.asl
@@ -25,8 +25,8 @@
* https://bugs.acpica.org/show_bug.cgi?id=1201
*/
OperationRegion (ITSS, SystemMemory,
- Add (R_PCH_PCR_ITSS_PIRQA_ROUT,
- Add (PCH_PCR_BASE_ADDRESS,
+ Add (PCR_ITSS_PIRQA_ROUT,
+ Add (CONFIG_PCR_BASE_ADDRESS,
ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)
Field (ITSS, ByteAcc, NoLock, Preserve)
{
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 4e7c951..78f31a8 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -15,11 +15,13 @@
* GNU General Public License for more details.
*/
+#include <intelblocks/pcr.h>
#include <soc/iomap.h>
#include <soc/irq.h>
+#include <soc/itss.h>
#include <soc/gpio_defs.h>
#include <soc/gpe.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
/* GPIO Controller */
#include "gpio.asl"
diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl
index efe8329..4b8576b 100644
--- a/src/soc/intel/skylake/acpi/pcr.asl
+++ b/src/soc/intel/skylake/acpi/pcr.asl
@@ -20,7 +20,8 @@
*/
Method (PCRB, 1, NotSerialized)
{
- Return (Add (PCH_PCR_BASE_ADDRESS, ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
+ Return (Add (CONFIG_PCR_BASE_ADDRESS,
+ ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
}
/*
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 60b22dc..ebd68f1 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,19 +18,35 @@
#include <chip.h>
#include <device/device.h>
#include <device/pci_def.h>
+#include <intelblocks/pcr.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
+#include <soc/itss.h>
#include <soc/lpc.h>
#include <soc/p2sb.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/smbus.h>
-/* Max PXRC registers in ITSS*/
-#define MAX_PXRC_CONFIG 0x08
+#define PCR_DMI_LPCLGIR1 0x2730
+#define PCR_DMI_LPCLGIR2 0x2734
+#define PCR_DMI_LPCLGIR3 0x2738
+#define PCR_DMI_LPCLGIR4 0x273c
+
+#define PCR_DMI_ACPIBA 0x27B4
+#define PCR_DMI_ACPIBDID 0x27B8
+#define PCR_DMI_PMBASEA 0x27AC
+#define PCR_DMI_PMBASEC 0x27B0
+#define PCR_DMI_TCOBASE 0x2778
+
+#define PCR_DMI_LPCIOD 0x2770
+#define PCR_DMI_LPCIOE 0x2774
+
+#define PCR_RTC_CONF 0x3400
+#define PCR_RTC_CONF_UCMOS_EN 0x4
/*
* Enable Prefetching and Caching.
@@ -69,7 +85,7 @@
device_t dev = PCH_DEV_P2SB;
/* Enable PCR Base address in PCH */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0, PCH_PCR_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
/* Enable P2SB MSE */
pci_write_config8(dev, PCI_COMMAND,
@@ -108,10 +124,10 @@
pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
/* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec);
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec);
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec);
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, config->gen1_dec);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, config->gen2_dec);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, config->gen3_dec);
+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, config->gen4_dec);
}
static void pch_interrupt_init(void)
@@ -140,8 +156,7 @@
pch_interrupt_routing[index] > 2 &&
pch_interrupt_routing[index] != 8 &&
pch_interrupt_routing[index] != 13) {
- pcr_write8(PID_ITSS,
- (R_PCH_PCR_ITSS_PIRQA_ROUT + index),
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + index,
pch_interrupt_routing[index]);
}
}
@@ -166,8 +181,8 @@
* to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
*/
reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBA, reg32);
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_ACPIBDID, 0x23A0);
+ pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
+ pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23A0);
}
static void soc_config_pwrmbase(void)
@@ -195,10 +210,10 @@
* implication of making sure the memory allocated to PWRMBASE to be
* 64KB in size.
*/
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA,
+ pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
(PCH_PWRM_BASE_ADDRESS >> 16)));
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEC, 0x800023A0);
+ pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023A0);
}
static void soc_config_tco(void)
@@ -222,8 +237,7 @@
* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
* to [SMBUS PCI offset 50h[15:5], 1].
*/
- pcr_write32(PID_DMI, R_PCH_PCR_DMI_TCOBASE,
- (TCO_BASE_ADDDRESS | (1 << 1)));
+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));
/* Program TCO timer halt */
tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
@@ -236,8 +250,7 @@
static void soc_config_rtc(void)
{
/* Enable upper 128 bytes of CMOS */
- pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, ~0,
- B_PCH_PCR_RTC_CONF_UCMOS_EN);
+ pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
}
static void enable_heci(void)
@@ -269,12 +282,12 @@
/* IO Decode Range */
lpc_en = COMA_RANGE | (COMB_RANGE << 4);
pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
- pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_en);
/* IO Decode Enable */
lpc_en = CNF1_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
- pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
}
void pch_early_init(void)
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index ff1687c..d51d179 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -18,12 +18,19 @@
#include <arch/io.h>
#include <console/uart.h>
#include <device/pci_def.h>
+#include <intelblocks/pcr.h>
#include <stdint.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
#include <soc/serialio.h>
#include <gpio.h>
+
+/* Serial IO UART controller legacy mode */
+#define PCR_SERIAL_IO_GPPRVRW7 0x618
+#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0)
+#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
+#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
@@ -64,8 +71,8 @@
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
- pcr_andthenor32(PID_SERIALIO,
- R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
+ pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
+ PCR_SIO_PCH_LEGACY_UART2);
gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index e923dcd..f489e4b 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -20,6 +20,8 @@
#include <console/console.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <stdlib.h>
@@ -27,13 +29,17 @@
#include <soc/me.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <soc/smbus.h>
#include <soc/spi.h>
#include <soc/systemagent.h>
-#include <device/pci.h>
-#include <chip.h>
+
+#define PCR_DMI_GCS 0x274C
+#define PCR_DMI_GCS_BILD (1 << 0)
+#define PSF_BASE_ADDRESS 0xA00
+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
{
@@ -62,8 +68,8 @@
pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
/* disable heci */
- pcr_andthenor32(PID_PSF1, PSF_BASE_ADDRESS + PCH_PCR_PSFX_T0_SHDW_PCIEN,
- ~0, PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
+ pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
+ PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
/* Remove the host accessing right to PSF register range. */
/* Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to [1, 1, 1, 1] */
@@ -171,8 +177,7 @@
/* Reads back for posted write to take effect */
pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL);
/* GCS reg of DMI */
- pcr_andthenor8(PID_DMI, R_PCH_PCR_DMI_GCS, 0xFF,
- B_PCH_PCR_DMI_GCS_BILD);
+ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
/* Bios Lock */
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index f65b1c9..afd65fc 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -21,7 +21,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <gpio.h>
-#include <soc/pcr.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
#include <soc/iomap.h>
#include <soc/pm.h>
@@ -83,6 +84,11 @@
"GPD",
};
+static inline void *gpio_community_regs(int port_id)
+{
+ return pcr_reg_address(port_id, 0);
+}
+
static inline size_t gpios_in_community(const struct gpio_community *comm)
{
/* max is inclusive */
@@ -128,7 +134,7 @@
/* Not all groups can be routed to SMI. However, the registers
* read as 0. In order to simplify the logic read everything from
* each community. */
- regs = pcr_port_regs(comm->port_id);
+ regs = gpio_community_regs(comm->port_id);
gpi_status_reg = (void *)®s[GPI_SMI_STS_OFFSET];
gpi_en_reg = (void *)®s[GPI_SMI_EN_OFFSET];
for (i = 0; i < num_grps; i++) {
@@ -214,7 +220,7 @@
uint32_t reg;
const struct gpio_community *comm = &communities[i];
- regs = pcr_port_regs(comm->port_id);
+ regs = gpio_community_regs(comm->port_id);
reg = read32(regs + MISCCFG_OFFSET);
reg &= ~misc_cfg_reg_mask;
@@ -234,7 +240,7 @@
if (comm == NULL)
return NULL;
- regs = pcr_port_regs(comm->port_id);
+ regs = gpio_community_regs(comm->port_id);
pad_relative = pad - comm->min;
@@ -254,7 +260,7 @@
if (comm == NULL)
return NULL;
- regs = pcr_port_regs(comm->port_id);
+ regs = gpio_community_regs(comm->port_id);
pad_relative = pad - comm->min;
@@ -301,7 +307,7 @@
comm = gpio_get_community(pad);
if (comm == NULL)
return;
- regs = pcr_port_regs(comm->port_id);
+ regs = gpio_community_regs(comm->port_id);
gpi_status_reg = (void *)®s[GPI_SMI_STS_OFFSET];
gpi_en_reg = (void *)®s[GPI_SMI_EN_OFFSET];
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index e2662cc..52ef640 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -23,9 +23,6 @@
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x4000000
-#define PCH_PCR_BASE_ADDRESS 0xfd000000
-#define PCH_PCR_BASE_SIZE 0x1000000
-
#define UART_DEBUG_BASE_ADDRESS 0xfe034000
#define UART_DEBUG_BASE_SIZE 0x1000
diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h
new file mode 100644
index 0000000..0681e9d
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/itss.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_SKL_ITSS_H
+#define SOC_INTEL_SKL_ITSS_H
+
+/* Max PXRC registers in ITSS*/
+#define MAX_PXRC_CONFIG 0x08
+
+/* PIRQA Routing Control Register*/
+#define PCR_ITSS_PIRQA_ROUT 0x3100
+/* PIRQB Routing Control Register*/
+#define PCR_ITSS_PIRQB_ROUT 0x3101
+/* PIRQC Routing Control Register*/
+#define PCR_ITSS_PIRQC_ROUT 0x3102
+/* PIRQD Routing Control Register*/
+#define PCR_ITSS_PIRQD_ROUT 0x3103
+/* PIRQE Routing Control Register*/
+#define PCR_ITSS_PIRQE_ROUT 0x3104
+/* PIRQF Routing Control Register*/
+#define PCR_ITSS_PIRQF_ROUT 0x3105
+/* PIRQG Routing Control Register*/
+#define PCR_ITSS_PIRQG_ROUT 0x3106
+/* PIRQH Routing Control Register*/
+#define PCR_ITSS_PIRQH_ROUT 0x3107
+/* ITSS Power reduction control */
+#define PCR_ITSS_ITSSPRC 0x3300
+
+#endif /* SOC_INTEL_SKL_ITSS_H */
diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h
deleted file mode 100644
index c83a267..0000000
--- a/src/soc/intel/skylake/include/soc/pcr.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_PCR_H_
-#define _SOC_PCR_H_
-
-/*
- * Primary to sideband (P2SB) for private configuration registers (PCR).
- */
-
-/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address. */
-#define PCR_PORTID_SHIFT 16
-#define PCR_OFFSET_SHIFT 0
-
-/* DMI Control Register */
-#define R_PCH_PCR_DMI_DMIC 0x2234
-#define B_PCH_PCR_DMI_DMIC_SRL (1 << 31)
-#define R_PCH_PCR_DMI_LPCLGIR1 0x2730
-#define R_PCH_PCR_DMI_LPCLGIR2 0x2734
-#define R_PCH_PCR_DMI_LPCLGIR3 0x2738
-#define R_PCH_PCR_DMI_LPCLGIR4 0x273c
-#define R_PCH_PCR_DMI_GCS 0x274C
-#define B_PCH_PCR_DMI_GCS_BILD (1 << 0)
-#define R_PCH_PCR_DMI_LPCIOD 0x2770
-#define R_PCH_PCR_DMI_LPCIOE 0x2774
-#define R_PCH_PCR_DMI_ACPIBA 0x27B4
-#define R_PCH_PCR_DMI_ACPIBDID 0x27B8
-#define R_PCH_PCR_DMI_PMBASEA 0x27AC
-#define R_PCH_PCR_DMI_PMBASEC 0x27B0
-#define R_PCH_PCR_DMI_TCOBASE 0x2778
-
-/* RTC configuration */
-#define R_PCH_PCR_RTC_CONF 0x3400
-#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK (1 << 4)
-#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK (1 << 3)
-#define B_PCH_PCR_RTC_CONF_RESERVED (1 << 31)
-#define B_PCH_PCR_RTC_CONF_UCMOS_EN 0x4
-
-/* ITSS PCRs*/
-/* PIRQA Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQA_ROUT 0x3100
-/* PIRQB Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQB_ROUT 0x3101
-/* PIRQC Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQC_ROUT 0x3102
-/* PIRQD Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQD_ROUT 0x3103
-/* PIRQE Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQE_ROUT 0x3104
-/* PIRQF Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQF_ROUT 0x3105
-/* PIRQG Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106
-/* PIRQH Routing Control Register*/
-#define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107
-/* ITSS Power reduction control */
-#define R_PCH_PCR_ITSS_ITSSPRC 0x3300
-# define CGE8254 (1 << 2)
-
-/* IO Trap PCRs */
-/* Trap status Register */
-#define R_PCH_PCR_PSTH_TRPST 0x1E00
-/* Trapped cycle */
-#define R_PCH_PCR_PSTH_TRPC 0x1E10
-/* Trapped write data */
-#define R_PCH_PCR_PSTH_TRPD 0x1E18
-
-/* Serial IO UART controller legacy mode */
-#define R_PCH_PCR_SERIAL_IO_GPPRVRW7 0x618
-#define SIO_PCH_LEGACY_UART0 (1 << 0)
-#define SIO_PCH_LEGACY_UART1 (1 << 1)
-#define SIO_PCH_LEGACY_UART2 (1 << 2)
-
-/*
- * P2SB port ids.
- */
-#define PID_PSTH 0x89
-#define PID_GPIOCOM3 0xAC
-#define PID_GPIOCOM2 0xAD
-#define PID_GPIOCOM1 0xAE
-#define PID_GPIOCOM0 0xAF
-#define PID_PSF1 0xBA
-#define PID_SCS 0xC0
-#define PID_RTC 0xC3
-#define PID_ITSS 0xC4
-#define PID_LPC 0xC7
-#define PID_SERIALIO 0xCB
-#define PID_DMI 0xEF
-
-#define PCH_PCR_PSFX_T0_SHDW_PCIEN 0x1C
-
-#define PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
-#define PSF_BASE_ADDRESS 0xA00
-
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
-#include <stdint.h>
-
-/* All these return 0 on success and < 0 on errror. */
-int pcr_read32(u8 pid, u16 offset, u32 *outdata);
-int pcr_read16(u8 pid, u16 offset, u16 *outdata);
-int pcr_read8(u8 pid, u16 offset, u8 *outdata);
-int pcr_write32(u8 pid, u16 offset, u32 indata);
-int pcr_write16(u8 pid, u16 offset, u16 indata);
-int pcr_write8(u8 pid, u16 offset, u8 indata);
-int pcr_andthenor32(u8 pid, u16 offset, u32 anddata, u32 ordata);
-int pcr_andthenor16(u8 pid, u16 offset, u16 anddata, u16 ordata);
-int pcr_andthenor8(u8 pid, u16 offset, u8 anddata, u8 ordata);
-
-/* Get the starting address of the port's registers. */
-uint8_t *pcr_port_regs(u8 pid);
-#endif /* if !defined(__ASSEMBLER__) && !defined(__ACPI__) */
-
-#endif /* _SOC_PCR_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h
new file mode 100644
index 0000000..71affd8
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/pcr_ids.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_SKL_PCR_H
+#define SOC_INTEL_SKL_PCR_H
+
+/*
+ * Port ids
+ */
+#define PID_PSTH 0x89
+#define PID_GPIOCOM3 0xAC
+#define PID_GPIOCOM2 0xAD
+#define PID_GPIOCOM1 0xAE
+#define PID_GPIOCOM0 0xAF
+#define PID_PSF1 0xBA
+#define PID_SCS 0xC0
+#define PID_RTC 0xC3
+#define PID_ITSS 0xC4
+#define PID_LPC 0xC7
+#define PID_SERIALIO 0xCB
+#define PID_DMI 0xEF
+
+#endif /* SOC_INTEL_SKL_PCR_H */
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index a81ff97..82207ed 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -30,11 +30,13 @@
#include <cpu/cpu.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
+#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <string.h>
#include <soc/acpi.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
+#include <soc/itss.h>
#include <soc/lpc.h>
#include <soc/nvs.h>
#include <soc/pch.h>
@@ -42,7 +44,7 @@
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/ramstage.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif
@@ -97,14 +99,14 @@
device_t irq_dev;
config_t *config = dev->chip_info;
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQA_ROUT, config->pirqa_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQB_ROUT, config->pirqb_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQC_ROUT, config->pirqc_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQD_ROUT, config->pirqd_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQE_ROUT, config->pirqe_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQF_ROUT, config->pirqf_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQG_ROUT, config->pirqg_routing);
- pcr_write8(PID_ITSS, R_PCH_PCR_ITSS_PIRQH_ROUT, config->pirqh_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQA_ROUT, config->pirqa_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQB_ROUT, config->pirqb_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQC_ROUT, config->pirqc_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQD_ROUT, config->pirqd_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQE_ROUT, config->pirqe_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQF_ROUT, config->pirqf_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQG_ROUT, config->pirqg_routing);
+ pcr_write8(PID_ITSS, PCR_ITSS_PIRQH_ROUT, config->pirqh_routing);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin = 0, int_line = 0;
@@ -157,13 +159,12 @@
static void clock_gate_8254(struct device *dev)
{
config_t *config = dev->chip_info;
- const uint32_t cge8254_mask = CGE8254;
+ const uint32_t cge8254_mask = (1 << 2);
if (!config->clock_gate_8254)
return;
- pcr_andthenor32(PID_ITSS, R_PCH_PCR_ITSS_ITSSPRC,
- ~cge8254_mask, cge8254_mask);
+ pcr_rmw32(PID_ITSS, PCR_ITSS_ITSSPRC, ~cge8254_mask, cge8254_mask);
}
static void lpc_init(struct device *dev)
@@ -190,7 +191,7 @@
* For this SOC, the range will be from 0FD000000h till FE7FFFFFh"
* Hence, use FD000000h as PCR_BASE
*/
- const u32 default_decode_base = PCH_PCR_BASE_ADDRESS;
+ const u32 default_decode_base = CONFIG_PCR_BASE_ADDRESS;
res = new_resource(dev, PCI_BASE_ADDRESS_0);
res->base = default_decode_base;
diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c
deleted file mode 100644
index 0b92d76..0000000
--- a/src/soc/intel/skylake/pcr.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/pcr.h>
-#include <soc/iomap.h>
-#include <console/console.h>
-
-static inline void *pcr_reg_address(u8 pid, u16 offset)
-{
- uintptr_t reg_addr;
-
- /* Create an address based off of port id and offset. */
- reg_addr = PCH_PCR_BASE_ADDRESS;
- reg_addr += ((uintptr_t)pid) << PCR_PORTID_SHIFT;
- reg_addr += ((uintptr_t)offset) << PCR_OFFSET_SHIFT;
-
- return (void *)reg_addr;
-}
-
-uint8_t *pcr_port_regs(u8 pid)
-{
- return pcr_reg_address(pid, 0);
-}
-
-/*
- * Read PCR register. (This is internal function)
- * It returns PCR register and size in 1/2/4 bytes.
- * The offset should not exceed 0xFFFF and must be aligned with size
- */
-static int pch_pcr_read(u8 pid, u16 offset, u32 size, void *data)
-{
- if ((offset & (size - 1)) != 0) {
- printk(BIOS_DEBUG,
- "PchPcrRead error. Invalid Offset: %x Size: %x",
- offset, size);
- return -1;
- }
- switch (size) {
- case 4:
- *(u32 *) data = read32(pcr_reg_address(pid, offset));
- break;
- case 2:
- *(u16 *) data = read16(pcr_reg_address(pid, offset));
- break;
- case 1:
- *(u8 *) data = read8(pcr_reg_address(pid, offset));
- break;
- default:
- return -1;
- }
- return 0;
-}
-
-int pcr_read32(u8 pid, u16 offset, u32 *outdata)
-{
- return pch_pcr_read(pid, offset, sizeof(u32), (u32 *)outdata);
-}
-
-int pcr_read16(u8 pid, u16 offset, u16 *outdata)
-{
- return pch_pcr_read(pid, offset, sizeof(u16), (u32 *)outdata);
-}
-
-int pcr_read8(u8 pid, u16 offset, u8 *outdata)
-{
- return pch_pcr_read(pid, offset, sizeof(u8), (u32 *)outdata);
-}
-
-/*
- * After every write one needs to perform a read an innocuous register to
- * ensure the writes are completed for certain ports. This is done for
- * all ports so that the callers don't need the per-port knowledge for
- * each transaction.
- */
-static inline void complete_write(void)
-{
- /* Read the general control and function disable register. */
- const size_t R_PCH_PCR_LPC_GCFD = 0x3418;
- read32(pcr_reg_address(PID_LPC, R_PCH_PCR_LPC_GCFD));
-}
-
-/*
- * Write PCR register. (This is internal function)
- * It returns PCR register and size in 1/2/4 bytes.
- * The offset should not exceed 0xFFFF and must be aligned with size
- */
-static int pch_pcr_write(u8 pid, u16 offset, u32 size, u32 data)
-{
- if ((offset & (size - 1)) != 0) {
- printk(BIOS_DEBUG,
- "PchPcrWrite error. Invalid Offset: %x Size: %x",
- offset, size);
- return -1;
- }
- /* Write the PCR register with provided data
- * Then read back PCR register to prevent from back to back write.
- */
- switch (size) {
- case 4:
- write32(pcr_reg_address(pid, offset), (u32) data);
- break;
- case 2:
- write16(pcr_reg_address(pid, offset), (u16) data);
- break;
- case 1:
- write8(pcr_reg_address(pid, offset), (u8) data);
- break;
- default:
- return -1;
- }
- /* Ensure the writes complete. */
- complete_write();
-
- return 0;
-}
-
-int pcr_write32(u8 pid, u16 offset, u32 indata)
-{
- return pch_pcr_write(pid, offset, sizeof(u32), indata);
-}
-
-int pcr_write16(u8 pid, u16 offset, u16 indata)
-{
- return pch_pcr_write(pid, offset, sizeof(u16), indata);
-}
-
-int pcr_write8(u8 pid, u16 offset, u8 indata)
-{
- return pch_pcr_write(pid, offset, sizeof(u8), indata);
-}
-
-/*
- * Write PCR register. (This is internal function)
- * It programs PCR register and size in 1/2/4 bytes.
- * The offset should not exceed 0xFFFF and must be aligned with size
- *
- * u8 defines as 8 bit Port ID that will be used when sending
- * transaction to sideband.
- */
-static int pcr_and_then_or(u8 pid, u16 offset, u32 size, u32 anddata,
- u32 ordata)
-{
- u8 status;
- u32 data32 = 0;
-
- status = pch_pcr_read(pid, offset, size, &data32);
- if (status != 0)
- return -1;
-
- data32 &= anddata;
- data32 |= ordata;
-
- status = pch_pcr_write(pid, offset, size, data32);
- return status;
-}
-
-int pcr_andthenor32(u8 pid, u16 offset, u32 anddata, u32 ordata)
-{
- return pcr_and_then_or(pid, offset, sizeof(u32), anddata, ordata);
-}
-
-int pcr_andthenor16(u8 pid, u16 offset, u16 anddata, u16 ordata)
-{
- return pcr_and_then_or(pid, offset, sizeof(u16), anddata, ordata);
-}
-
-int pcr_andthenor8(u8 pid, u16 offset, u8 anddata, u8 ordata)
-{
- return pcr_and_then_or(pid, offset, sizeof(u8), anddata, ordata);
-}
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 003c462..64df186 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -24,6 +24,7 @@
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/cpu.h>
+#include <intelblocks/pcr.h>
#include <pc80/mc146818rtc.h>
#include <reg_script.h>
#include <string.h>
@@ -33,7 +34,7 @@
#include <soc/pmc.h>
#include <soc/pm.h>
#include <cpu/x86/smm.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
#include <soc/ramstage.h>
#include <vboot/vbnv.h>
#include <vboot/vbnv_layout.h>
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 382bdfc..e6f6959 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -21,21 +21,30 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
-#include <device/pci_def.h>
#include <cpu/x86/smm.h>
-#include <spi-generic.h>
+#include <device/pci_def.h>
#include <elog.h>
+#include <intelblocks/pcr.h>
#include <pc80/mc146818rtc.h>
+#include <spi-generic.h>
#include <soc/flash_controller.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pch.h>
-#include <soc/pcr.h>
+#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/smm.h>
+
+/* IO Trap PCRs */
+/* Trap status Register */
+#define PCR_PSTH_TRPST 0x1E00
+/* Trapped cycle */
+#define PCR_PSTH_TRPC 0x1E10
+/* Trapped write data */
+#define PCR_PSTH_TRPD 0x1E18
static u8 smm_initialized = 0;
@@ -425,16 +434,17 @@
static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
- u32 trap_sts, trap_cycle;
+ u32 trap_cycle;
u32 data, mask = 0;
+ u8 trap_sts;
int i;
/* TRSR - Trap Status Register */
- pcr_read32(PID_PSTH, R_PCH_PCR_PSTH_TRPST, &trap_sts);
+ trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);
/* Clear trap(s) in TRSR */
- pcr_write8(PID_PSTH, R_PCH_PCR_PSTH_TRPST, trap_sts);
+ pcr_write8(PID_PSTH, PCR_PSTH_TRPST, trap_sts);
/* TRPC - Trapped cycle */
- pcr_read32(PID_PSTH, R_PCH_PCR_PSTH_TRPC, &trap_cycle);
+ trap_cycle = pcr_read32(PID_PSTH, PCR_PSTH_TRPC);
for (i = 16; i < 20; i++) {
if (trap_cycle & (1 << i))
mask |= (0xff << ((i - 16) << 2));
@@ -458,7 +468,7 @@
if (!(trap_cycle & (1 << 24))) { /* It's a write */
printk(BIOS_DEBUG, "SMI1 command\n");
/* Trapped write data */
- pcr_read32(PID_PSTH, R_PCH_PCR_PSTH_TRPD, &data);
+ data = pcr_read32(PID_PSTH, PCR_PSTH_TRPD);
data &= mask;
}
}
@@ -475,7 +485,7 @@
if (!(trap_cycle & (1 << 24))) {
/* Write Cycle */
- pcr_read32(PID_PSTH, R_PCH_PCR_PSTH_TRPD, &data);
+ data = pcr_read32(PID_PSTH, PCR_PSTH_TRPD);
printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
}
#undef IOTRAP
--
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Gerrit-MessageType: merged
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