[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945/raminit.c: Refactor tRD selection

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18354 )

Change subject: nb/intel/i945/raminit.c: Refactor tRD selection
......................................................................


Patch Set 12:

(3 comments)

https://review.coreboot.org/#/c/18354/12//COMMIT_MSG
Commit Message:

PS12, Line 11: Some values for tRD on 800 and 1067MHz FSB were set wrong because the
             : CAS/Freq selection was wrong.
> Could you give one example for each please?
Yes CAS was typically selected to low. When increasing CAS to correct value it increased tRD too much because of incorrect lookup table. Will clarify this in commit message.


Line 14: PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5
> Nice. But on what board?
ga-945gcm-s2l. Will add it.


https://review.coreboot.org/#/c/18354/12/src/northbridge/intel/i945/raminit.c
File src/northbridge/intel/i945/raminit.c:

PS12, Line 1834: 	/*
               : 	 * tRD is the delay the memory controller is waiting on the FSB,
               : 	 * in mclk domain.
               : 	 * This parameter is important for stability and performance.
               : 	 * Those values might not be optimal but seem stable.
               : 	 */
               : 	tRD_min = sysinfo->cas;
               : 	switch (sysinfo->fsb_frequency) {
               : 	case 533: break;
               : 	case 667: tRD_min += 1; break;
               : 	case 800: tRD_min += 2; break;
               : 	case 1066: tRD_min += 3; break;
               : 	}
> `checkpatch.pl` results [1]:
ok


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Gerrit-MessageType: comment
Gerrit-Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94
Gerrit-PatchSet: 12
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
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