[coreboot-gerrit] Change in coreboot[master]: drivers/storage: Add SD/MMC/eMMC support

Lee Leahy (Code Review) gerrit at coreboot.org
Fri Apr 7 23:35:12 CEST 2017 

Hello build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/19208

to look at the new patch set (#2).

Change subject: drivers/storage: Add SD/MMC/eMMC support
......................................................................

drivers/storage: Add SD/MMC/eMMC support

drivers/storage: Add depthcharge SD/EMMC driver

Copy the SD/MMC driver from depthcharge revision
eb583fa82e697a97cb13a2906fcda6e2470c7623 into coreboot.

Removed #include "config.h" from mmc.c to allow the lint tests to pass.

TEST=Does not build

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

include/device: Move mmc.h and sdhci.h into include/device

Move include files from drivers/storage into include/device.
Rename mmc.h to storage.h.

TEST=None

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Get SD/MMC driver to build

Add the Kconfig and Makefile and make necessary edits to get the code to
build.

TEST=Build for reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Support PCI SD/MMC controllers

Add support to initialize a PCI controller.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Fix formatting issues detected by checkpatch

Fix the following errors and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
ERROR: switch and case should be at the same indent
ERROR: spaces prohibited around that '->' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)
WARNING: line over 80 characters
WARNING: please, no spaces at the start of a lineWARNING: please, no spaces at the start of a line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: suspect code indent for conditional statements (24, 28)

These issues should not change the binary.

TEST=None

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Fix data flow issues detected by checkpatch

Fix the following error and warnings detected by checkpatch.pl:

ERROR: trailing statements should be on next line
WARNING: else is not generally useful after a break or return
WARNING: long udelay - prefer mdelay; see arch/arm/include/asm/delay.h

These change are expected to change the binary.

The following errors detected by checkpatch are false positives:
ERROR: need consistent spacing around '*' (ctx:WxV)
ERROR: Macros with complex values should be enclosed in parentheses

TEST=None

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

include/device: Fix MMC voltage mask

Add the missing voltage (MMC_VDD_35_36) into the voltage mask.

TEST=None

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Rename mmc_* debug macros to sd_mmc_*

Rename the mmc_debug, mmc_trace and mmc_error to sd_mmc_debug,
sd_mmc_trace and sd_mmc_error.  Replace printf with sd_mmc_error.

TEST=Build and run on galileo gen2

Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>

drivers/storage: Add sdhc_* debug macros

Add sdhc_debug, sdhc_trace and sd_error macros.
Add Kconfig values to enable debugging and Trace.

TEST=Build and run on Galileo Gen2

Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>

drivers/storage: Add tracing support to SDHCI driver

Add tracing and debug support to the SDHCI driver
* Replace printf and printk with sd_error
* Display the interrupt status for timeout errors
* Add tracing to display the commands and responses
* Add debug to display high level state of the SD/MMC device and bus

TEST=Build and run on Galileo Gen2

Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>

drivers/storage: Allow SOC to override more controller features

Instead of converting from SDHCI_PLATFORM_* to SDHCI_QUIRK_* to
MMC_MODE_*, call the SOC back with the SdhciHost and MmcCtrlr structures
to allow the necessary updates to support the controller quirks.

TEST=Build for reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Split out ADMA support

On x86 sysems DMA is only supported to RAM, early stages must do
programed I/O to send/receive data from the SD/MMC device.  Use Kconfig
values to enable DMA during early boot stages.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Move 1V8 support into soc routine

Eliminate SDHCI_PLATFORM_EMMC_1V8_POWER and SDHCI_QUIRK_EMMC_1V8_POWER
and instead let the platform set MMC_MODE_1V8_VDD in
host->mmc_ctrlr.caps.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Move HS400 support into soc routine

Eliminate SDHCI_PLATFORM_SUPPORTS_HS400ES and
SDHCI_QUIRK_SUPPORTS_HS400ES and instead let the platform set
MMC_MODE_HS400ES and possibly MMC_MODE_HS400.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Rework clock handling

* Eliminate SDHCI_PLATFORM_NO_CLK_BASE and
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
* Move the clock values into the controller structure
* Use bus_hz as actual bus frequency
* Platform overrides clock frequencies using soc_sdhci_quirks
* Use MIN and MAX to insure clock value is in the supported range
* Remove loop for computing divisor for Version 3 controllers
* Only stop and restart the clock when the clock frequency changes
* Display clock values after the call to soc_sdhci_quirks

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Switch to using a common symbol for the controller

Change the various controller references to use mmc_ctrlr for the
controller.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Update the voltage handling

Update the voltage handling:
* Eliminate SDHCI_QUIRK_BROKEN_VOLTAGE
* Eliminate hardcoded_voltage
* Platforms adjust the voltages in soc_sdhci_quirks
* Only change the power when necessary

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Update modes of operation

Update the modes of operation:
* Eliminate SDHCI_PLATFORM_NO_EMMC_HS200 and SDHCI_QUIRK_NO_EMMC_HS200
* Platform can use soc_sdhci_quirks to update operating modes

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Move DMA fields into MmcCtrlr

Update DMA support:
* Move controller structures into sdhci.h
* Move ADMA structures and fields into MmcCtrlr

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Update bus width support

Rework the bus width support:
* Simplify the bus width logic
* Display bus width changes when they happen

BRANCH=none
BUG=None
TEST=None

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Change MMC_TIMING_* to BUS_TIMING_*

rename MMC_TIMING_* to BUS_TIMING_* and simplify its use by replacing an
if chain with an array.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Rename MMC_MODE_ to DRVR_CAP

Rename MMC_MODE_* to DRVR_CAP_* since these values change the behavior
of the driver and not all of them are MMC specific.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Move quirks into caps

Use a single field to handle driver quirks and capabilities:

* Migrate host->quirk bits into mmc_ctrlr->caps
* Rename SDHCI_QUIRK_* to DRVR_CAP_*
* Rename SDHCI_PALTFORM_REMOVABLE to DRVR_CAP_REMOVABLE
* No need to pass in platform_info
* Host sets quirks and removable bit by setting the corresponding
DRVR_CAP_* bit in soc_sdhci_quirks

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Associate removeable with the controller

The platform construction determines whether a SD/MMC device is
removable or embedded.  Migrate the removable flag from the host to the
controller.  This enables the mainboard code to indicate if the SD/MMC
device is socketed or soldered onto the board.

TEST=Build and run on Galileo Gen2

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Statically allocate MmcMedia

Prepare for use in earlier stages.  Statically allocate MmcMedia instead
of using dynamic allocation.  Rework sdhci_update to make it media
independent.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Eliminate the SdhciHost structure

Replace the SdhciHost structure with the MmcCtrlr structure.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

driver/storage: Support other controller types

Split the code to allow for other SD/MMC controllers by using three data
structures:
* SdhciCtrlr - SDHCI controller specific data, devices/sdhci.h
* SdMmcCtrlr - Controller independent data, devices/sd_mmc_ctrlr.h
* MmcMedia - eMMC/MMC card specific data, devices/mmc.h

The specific changes:
* Move controller independent structures and definitions into
sd_mmc_ctrlr.h
* Pass MmcMedia as first parameter to all external mmc routines
* Use ctrlr to reference the SdMmcCtrlr data structure in all sources
* Use sdhci_ctrlr to reference the SdhciCtrlr data structure in the
SDHCI driver
* Move the controller independent fields into SdMmcCtrlr
* Remove the media field from the controller structures
* MmcMedia data structure now points to generic controller (SdMmcCtrlr)
* SdMmcCtrlr structure at beginning of SdhciCtrlr structure to allow
recast
* Removed mmc_busy_wait_io and mmc_busy_wait_io_until from mmc.c

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Split out erase and write support

Split out erase and write support:
* Move erase support into card_erase.c
* Move write support into card_write.c
* Add Kconfig values to enable erase and write support during bootblock
& verstage

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Remove typedefs and bumppy case

Update the code to be more consistent with the coreboot coding style:

* Remove the typedefs from the code
* Replace MmcCommand with struct mmc_command
* Replace MmcData with struct mmc_data
* Replace SdMmcCtrlr with struct sd_mmc_ctrlr
* Replace MmcMedia with struct flash_media
* Replace lba_t with uint64_t
* Replace SdhciAdma with struct sdhci_adma
* Replace SdhciAdma64 with struct sdhci_adma64
* Replace SdhciCtrlr with struct sdhci_ctrlr
* Replace pcidev_t with uint32_t

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Only expose calling APIs

Migrate driver specific constants, routines and data structures into the
storage directory.

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Split UP mmc.c

Divide up mmc.c into the following modules:
* mmc.c - MMC specific code
* sd.c - SD specific code
* sd_mmc.c - Common MMC and SD initialization code, may support SDIO
             in the future.
* storage.c - Storage card/device specific code

TEST=Build and run on reef and Galileo Gen2

Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>

drivers/storage: Update debug and error messages

Update the error messages:
* Remove prefix
* Make them type independent
* Remove a couple debug messages

TEST=Build and run on reef

Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>

drivers/storage: Add partition support

Acknowledge that embedded MMC devices support a physical breakup of the
storage device into hardware enforced partitions.  Enable the caller to
select the desired partition to be used for read/write/erase operations.

Capacity is now partition based.  Replace block_count with the capacity
array.  Since read and write sizes may be different, validate the access
using the capacity values.

TEST=Build and run on reef

Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
A src/drivers/storage/Kconfig
A src/drivers/storage/Makefile.inc
A src/drivers/storage/bouncebuf.c
A src/drivers/storage/bouncebuf.h
A src/drivers/storage/mmc.c
A src/drivers/storage/mmc.h
A src/drivers/storage/pci_sdhci.c
A src/drivers/storage/sd.c
A src/drivers/storage/sd_mmc.c
A src/drivers/storage/sd_mmc.h
A src/drivers/storage/sdhci.c
A src/drivers/storage/sdhci.h
A src/drivers/storage/sdhci_adma.c
A src/drivers/storage/storage.c
A src/drivers/storage/storage.h
A src/drivers/storage/storage_erase.c
A src/drivers/storage/storage_write.c
A src/include/device/sd_mmc_ctrlr.h
A src/include/device/sdhci.h
A src/include/device/storage.h
20 files changed, 4,122 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/19208/2
-- 
To view, visit https://review.coreboot.org/19208
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)

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