[coreboot-gerrit] Change in coreboot[master]: soc/intel/quark: Add SD/MMC test support
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Apr 7 21:42:20 CEST 2017
Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/19211 )
Change subject: soc/intel/quark: Add SD/MMC test support
......................................................................
soc/intel/quark: Add SD/MMC test support
* Add SD/MMC function
* Build SD/MMC driver
* Add ramstage SD card testing
* Select SDHC_DEBUG and SDHC_TRACE
* Don't pass in clock frequencies
* Use ctrlr instead of mmc_ctrlr
* Don't pass platform_info
* Move removable into ctrlr->caps
* Pass in MmcMedia
* Switch to mmc_ctrlr
* Use split driver
* Remove typedefs
* Add SD test code to romstage
* Switch to use storage_setup_media
TEST=Build and run on Galileo Gen2
Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
M src/soc/intel/quark/Kconfig
M src/soc/intel/quark/Makefile.inc
M src/soc/intel/quark/include/soc/iomap.h
M src/soc/intel/quark/include/soc/pci_devs.h
A src/soc/intel/quark/include/soc/sd_test.h
M src/soc/intel/quark/romstage/fsp2_0.c
A src/soc/intel/quark/sd.c
A src/soc/intel/quark/sd_test.c
8 files changed, 239 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/19211/1
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index c697b56..a4ed96a 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -304,4 +304,17 @@
hex
default 0x8000
+#####
+# Test support
+#####
+
+config STORAGE_TEST
+ bool "Test SD/MMC/eMMC card or device access"
+ default y
+ select DRIVERS_STORAGE
+ select SDHCI_CONTROLLER
+ help
+ Read block 0 from each parition of the storage device. User must
+ also enable one or both of DRIVERS_STORAGE_SD or DRIVERS_STORAGE_MMC.
+
endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 1d66e6b..88ea552 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -56,10 +56,19 @@
ramstage-y += northcluster.c
ramstage-y += reg_access.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+ramstage-y += sd.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+ifeq ($(CONFIG_STORAGE_TEST),y)
+bootblock-y += sd_test.c
+verstage-y += sd_test.c
+romstage-y += sd_test.c
+postcar-y += sd_test.c
+ramstage-y += sd_test.c
+endif
+
CPPFLAGS_common += -I$(src)/soc/intel/quark
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
index 1224bcc..de81a1a 100644
--- a/src/soc/intel/quark/include/soc/iomap.h
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -28,6 +28,9 @@
#define I2C_BASE_ADDRESS 0xa0020000
#define GPIO_BASE_ADDRESS 0xa0021000
+/* Temporary BAR for SD controller */
+#define SD_BASE_ADDRESS 0xa0022000
+
/*
* I/O port address space
*/
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 2ddc214..3602a7d 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -34,8 +34,10 @@
/* IO Fabric 1 */
#define SIO1_DEV 0x14
+#define SD_MMC_DEV SIO1_DEV
#define HSUART0_DEV SIO1_DEV
#define HSUART1_DEV SIO1_DEV
+#define SD_MMC_FUNC 0
#define HSUART0_FUNC 1
#define USB_DEV_PORT_FUNC 2
#define EHCI_FUNC 3
diff --git a/src/soc/intel/quark/include/soc/sd_test.h b/src/soc/intel/quark/include/soc/sd_test.h
new file mode 100644
index 0000000..44e0b13
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/sd_test.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyrigit 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SD_TEST_H__
+#define __SD_TEST_H__
+
+#include <device/device.h>
+#include <device/pci.h>
+
+#ifdef __SIMPLE_DEVICE__
+#define dev_t uintptr_t
+#else
+#define dev_t device_t
+#endif /* __SIMPLE_DEVICE__ */
+
+uint32_t sd_test_init(dev_t dev, uint32_t *previous_bar,
+ uint16_t *previous_command);
+void sd_test(uint32_t bar);
+void sd_test_complete(dev_t dev, uint32_t previous_bar,
+ uint16_t previous_command);
+
+#endif /* __SD_TEST_H__ */
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index d03545d..e258268 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -19,10 +19,12 @@
#include "../chip.h"
#include <cpu/x86/cache.h>
#include <fsp/util.h>
+#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/reg_access.h>
+#include <soc/sd_test.h>
asmlinkage void *car_stage_c_entry(void)
{
@@ -34,6 +36,21 @@
post_code(0x20);
console_init();
+ if (IS_ENABLED(CONFIG_STORAGE_TEST)) {
+ uint32_t bar;
+ dev_t dev;
+ uint32_t previous_bar;
+ uint16_t previous_command;
+
+ /* Enable the SD/MMC controller and run the test. Restore
+ * the BAR and command registers upon completion.
+ */
+ dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC);
+ bar = sd_test_init(dev, &previous_bar, &previous_command);
+ sd_test(bar);
+ sd_test_complete(dev, previous_bar, previous_command);
+ }
+
/* Initialize DRAM */
s3wake = fill_power_state() == ACPI_S3;
fsp_memory_init(s3wake);
diff --git a/src/soc/intel/quark/sd.c b/src/soc/intel/quark/sd.c
new file mode 100644
index 0000000..9085239
--- /dev/null
+++ b/src/soc/intel/quark/sd.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyrigit 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/sdhci.h>
+#include <device/storage.h>
+#include <soc/sd_test.h>
+
+static void init(struct device *dev)
+{
+ /* Run the SD test */
+ if (IS_ENABLED(CONFIG_SD_CARD_TEST)) {
+ uint32_t bar;
+ uint32_t previous_bar;
+ uint16_t previous_command;
+
+ bar = sd_test_init(dev, &previous_bar, &previous_command);
+ sd_test(bar);
+ sd_test_complete(dev, previous_bar, previous_command);
+ }
+}
+
+static const struct device_operations device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = init,
+};
+
+static const struct pci_driver pmc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x08A7,
+};
diff --git a/src/soc/intel/quark/sd_test.c b/src/soc/intel/quark/sd_test.c
new file mode 100644
index 0000000..f42a133
--- /dev/null
+++ b/src/soc/intel/quark/sd_test.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyrigit 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/sdhci.h>
+#include <device/storage.h>
+#include <lib.h>
+#include <soc/sd_test.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/sd_test.h>
+
+uint32_t sd_test_init(dev_t dev, uint32_t *previous_bar,
+ uint16_t *previous_command)
+{
+ uint32_t bar;
+
+ /* Display the vendor/device IDs */
+ printk(BIOS_DEBUG, "Vendor ID: 0x%04x, Device ID: 0x%04x\n",
+ pci_read_config16(dev, PCI_VENDOR_ID),
+ pci_read_config16(dev, PCI_DEVICE_ID));
+
+ /* Set the temporary base address */
+ bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ *previous_bar = bar;
+ bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+ if (!bar) {
+ bar = SD_BASE_ADDRESS;
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar);
+ }
+
+ /* Enable the SD/MMC controller */
+ *previous_command = pci_read_config16(dev, PCI_COMMAND);
+ pci_write_config16(dev, PCI_COMMAND, *previous_command
+ | PCI_COMMAND_MEMORY);
+
+ /* Return the controller address */
+ return bar;
+}
+
+void sd_test_complete(dev_t dev, uint32_t previous_bar,
+ uint16_t previous_command)
+{
+ pci_write_config16(dev, PCI_COMMAND, previous_command);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, previous_bar);
+}
+
+void sd_test(uint32_t bar)
+{
+ uint64_t blocks_read;
+ uint8_t buffer[512];
+ int err;
+ const char *name;
+ unsigned int partition;
+ unsigned int previous_partition;
+ struct sdhci_ctrlr sdhci_ctrlr;
+ struct storage_media media;
+
+ /* Initialize the controller */
+ printk(BIOS_DEBUG, "Initializing the SD/MMC controller\n");
+ err = sdhci_controller_init(&sdhci_ctrlr, (void *)bar);
+ if (err) {
+ printk(BIOS_ERR,
+ "ERROR: SD controller init failed, err = %d\n", err);
+ return;
+ }
+
+ /* Initialize the SD/MMC/eMMC card or device */
+ printk(BIOS_DEBUG, "Initializing the device\n");
+ err = storage_setup_media(&media, &sdhci_ctrlr.sd_mmc_ctrlr);
+ if (err) {
+ printk(BIOS_ERR,
+ "ERROR: Device init failed, err = %d\n", err);
+ return;
+ }
+
+ /* Save the current partition */
+ previous_partition = storage_get_current_partition(&media);
+
+ /* Read block 0 from each partition */
+ for (partition = 0; partition < ARRAY_SIZE(media.capacity);
+ partition++) {
+ if (media.capacity[partition] == 0)
+ continue;
+ name = storage_partition_name(&media, partition);
+ printk(BIOS_DEBUG, "%s%sReading block 0\n", name,
+ name[0] ? ": " : "");
+ err = storage_set_partition(&media, previous_partition);
+ if (err)
+ continue;
+ blocks_read = storage_block_read(&media, 0, 1, &buffer);
+ if (blocks_read)
+ hexdump(buffer, sizeof(buffer));
+ }
+
+ /* Restore the previous partition */
+ storage_set_partition(&media, previous_partition);
+}
--
To view, visit https://review.coreboot.org/19211
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
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