[coreboot-gerrit] Change in coreboot[master]: mainboard/google/reef: Add eMMC test support

[Lee Leahy (Code Review)]

Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/19210 )

Change subject: mainboard/google/reef: Add eMMC test support
......................................................................

mainboard/google/reef: Add eMMC test support

Specify the controller capabilities for the eMMC device.  The new emmc.c
module is only consumed when the SD/MMC driver is enabled, otherwise it
is discarded by the linker.  Currently limit bootblock, verstage and
romstage to 50 MHz.

TEST=Build and run on reef

Change-Id: I5bb7923e1dea40673e287b17f92e27735c20402a
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
M src/mainboard/google/reef/Makefile.inc
A src/mainboard/google/reef/emmc.c
2 files changed, 41 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/19210/1

diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc
index ac654fb..4ac2b18 100644
--- a/src/mainboard/google/reef/Makefile.inc
+++ b/src/mainboard/google/reef/Makefile.inc
@@ -1,15 +1,19 @@
 bootblock-y += bootblock.c
 bootblock-y += ec.c
+bootblock-y += emmc.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += boardid.c
+romstage-y += emmc.c
 
 ramstage-y += boardid.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
+ramstage-y += emmc.c
 ramstage-y += mainboard.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-y += emmc.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 subdirs-y += variants/baseboard
diff --git a/src/mainboard/google/reef/emmc.c b/src/mainboard/google/reef/emmc.c
new file mode 100644
index 0000000..aa0b56b
--- /dev/null
+++ b/src/mainboard/google/reef/emmc.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyrigit 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/sdhci.h>
+#include <device/storage.h>
+
+void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr)
+{
+	/* Display things before they change */
+	printk(BIOS_DEBUG, "0x%08x: ctrlr->caps\n", ctrlr->caps);
+
+	/* Specify the additional driver support */
+	ctrlr->caps |= DRVR_CAP_1V8_VDD
+		| DRVR_CAP_HS400
+		| DRVR_CAP_HS400ES;
+
+	/* Limit operation in early stages */
+	if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) {
+		ctrlr->caps &= ~(DRVR_CAP_HS400
+			| DRVR_CAP_HS400ES
+			| DRVR_CAP_HS_200MHz);
+		ctrlr->f_max = CLOCK_50MHZ;
+	}
+}

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I5bb7923e1dea40673e287b17f92e27735c20402a
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>