[coreboot-gerrit] Change in coreboot[master]: google/fizz: Configure Memory

[Shelley Chen (Code Review)]

Shelley Chen has uploaded a new change for review. ( https://review.coreboot.org/19205 )

Change subject: google/fizz: Configure Memory
......................................................................

google/fizz: Configure Memory

Read DRAM spd and populate MemorySpdPtr fields
in UPD data structure for FSP.

BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a

Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/fizz/romstage.c
1 file changed, 69 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/19205/1

diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index 8bcfcd3..9e57751 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -13,10 +13,69 @@
  * GNU General Public License for more details.
  */
 
+#include <console/console.h>
 #include <soc/romstage.h>
 #include <string.h>
+#include <spd_bin.h>
 
 #include <fsp/soc_binding.h>
+
+#define SPD_LEN                 384
+#define SPD_DRAM_TYPE           2
+#define SPD_DENSITY_BANKS       4
+#define SPD_ADDRESSING          5
+#define SPD_PART_OFF            329
+#define SPD_PART_LEN            20
+#define SPD_MANU_OFF            350
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+        const int spd_banks[16] = { 4,  8, -1, -1,  8, 16, -1, -1,
+				   16, 32, -1, -1, -1, -1, -1, -1 };
+	const int spd_capmb[8] = {  1,  2,  4,  8, 16, 32, 64,  0 };
+	const int spd_rows[8]  = { 12, 13, 14, 15, 16, -1, -1, -1 };
+	const int spd_cols[8]  = {  9, 10, 11, 12, -1, -1, -1, -1 };
+	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
+	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
+	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	char spd_name[SPD_PART_LEN+1] = { 0 };
+
+	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 0xF];
+	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+	int rows  = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+	int cols  = spd_cols[spd[SPD_ADDRESSING] & 7];
+	int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+	int devw  = spd_devw[spd[SPD_ORGANIZATION] & 7];
+	int busw  = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+	/* Module type */
+	printk(BIOS_INFO, "SPD: module type is ");
+	switch (spd[SPD_DRAM_TYPE]) {
+	case SPD_DRAM_DDR4:
+		printk(BIOS_INFO, "DDR4\n");
+		break;
+	default:
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		break;
+	}
+
+	/* Module Part Number */
+	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+	spd_name[SPD_PART_LEN] = 0;
+	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+	printk(BIOS_INFO,
+		"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
+		banks, ranks, rows, cols, capmb);
+	printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+		devw, busw);
+
+	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+		printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+			capmb / 8 * busw / devw * ranks);
+	}
+}
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -28,4 +87,14 @@
 
 	memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
 	memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
+
+	/* Read spd block to get memory config */
+	struct spd_block blk;
+	mem_cfg->DqPinsInterleaved = 1;
+	get_spd_smbus(&blk);
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+
+	mainboard_print_spd_info(blk.spd_array[0]);
 }

-- 
To view, visit https://review.coreboot.org/19205
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen at google.com>