[coreboot-gerrit] Change in coreboot[master]: intel/soc/apollolake: [WIP]Use intel/common/uart driver

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19204 )

Change subject: intel/soc/apollolake: [WIP]Use intel/common/uart driver
......................................................................

intel/soc/apollolake: [WIP]Use intel/common/uart driver

Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/include/soc/uart.h
M src/soc/intel/apollolake/uart_early.c
4 files changed, 17 insertions(+), 33 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/19204/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 24e820c..4870e2d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -52,8 +52,8 @@
 	select SOC_INTEL_COMMON_ACPI
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
-	select SOC_INTEL_COMMON_BLOCK_LPSS
 	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_SMI
 	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index dc17b15..f242cc7 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -151,7 +151,7 @@
 
 	/* Prepare UART for serial console. */
 	if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
-		soc_console_uart_init();
+		pch_uart_init();
 
 	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
 		tpm_enable();
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index c7ba4a6..905368c 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -18,9 +18,14 @@
 #ifndef _SOC_APOLLOLAKE_UART_H_
 #define _SOC_APOLLOLAKE_UART_H_
 
-void lpss_console_uart_init(void);
+/*
+* M and N divisor values for clock frequency configuration. 
+* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
+*/
+#define CLK_M_VAL	0x025a
+#define CLK_N_VAL	0x7fff
 
 /* Initialize the console UART including the pads for the configured UART. */
-void soc_console_uart_init(void);
+void pch_uart_init(void);
 
 #endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 0a32b71..311e580 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -17,7 +17,7 @@
 
 #include <console/uart.h>
 #include <device/pci.h>
-#include <intelblocks/lpss.h>
+#include <intelblocks/uart.h>
 #include <soc/gpio.h>
 #include <soc/uart.h>
 #include <soc/pci_devs.h>
@@ -29,32 +29,6 @@
 	if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)
 		return 1;
 	return 0;
-}
-
-void lpss_console_uart_init(void)
-{
-	uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
-	device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
-
-	if (invalid_uart_for_console())
-		return;
-
-	/* Enable BAR0 for the UART -- this is where the 8250 registers hide */
-	pci_write_config32(uart, PCI_BASE_ADDRESS_0, base);
-
-	/* Enable memory access and bus master */
-	pci_write_config32(uart, PCI_COMMAND,
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-	/* Take UART out of reset */
-	lpss_reset_release(base);
-
-	/*
-	 * Set M and N divisor inputs and enable clock. These values
-	 * get us a 1.836 MHz clock (ideally we want 1.843 MHz)
-	 */
-	lpss_clk_update(base, 0x025a, 0x7fff);
-
 }
 
 uintptr_t uart_platform_base(int idx)
@@ -69,8 +43,11 @@
 	PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1),		/* UART2 TX */
 };
 
-void soc_console_uart_init(void)
+void pch_uart_init(void)
 {
+	uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+	device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
 	/* Get a 0-based pad index. See invalid_uart_for_console() above. */
 	const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
 
@@ -80,5 +57,7 @@
 	/* Configure the 2 pads per UART. */
 	gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
 
-	lpss_console_uart_init();
+	/* Program UART2 BAR0, command, reset and clock register */
+	uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);
+
 }

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>